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E1Mx16 Device
E1 Mapper 16-Channel TXC-04216 DATA SHEET FEATURES
* Add/drop sixteen 2.048 Mbit/s signals from an STM-1 VC-4/AU-3, STS-3, or an STS-1 * Independent add and drop bus timing modes * Selectable HDB3 positive/negative rail or NRZ E1 interface. Performance counter provided for illegal coding violations. * Digital desynchronizers * J2 16-byte ETSI trail trace comparison * Drop buses are monitored for parity, loss of clock, upstream AIS and H4 multiframe errors * TU Tandem Connection ETSI message processing and generation * Performance counters are provided for TU/VT pointer movements, BIP-2 errors and Far End Block Errors (REIs) * TU/VTs are monitored for Loss Of Pointer, New Data Flags (NDFs), AIS, Remote Defect Indication (RDI), and size errors (S-bits) * V5 Byte Signal Label Mismatch and Unequipped detection * E1 facility and line loopbacks, generation of BIP-2 and REI errors, and send RDI capability * Intel / Motorola compatible microprocessor bus interface with interrupt capability * Programmable internal RISC processor implements VT-POH and VT-alarm handling * Boundary scan capability (IEEE 1149.1) * Single +5V, 5% power supply * 388-lead plastic ball grid array (35 x 35 mm) package
DESCRIPTION
The E1 Mapper 16-Channel device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. Four field-proven QE1M Quad E1 Mapper chips are interconnected in a single compact package to permit higher application board densities. Sixteen E1 2.048 Mbit/s signals are mapped to and from asynchronous Tributary Unit-12s (TU-12s) or Virtual Tributary 2s (VT2s). The E1Mx16 interfaces to a multiple-segment, byte-parallel SDH/SONET-formatted Telecom Bus at the 19.44 Mbit/s byte rate for STM-1/STS-3 operation or at the 6.48 Mbit/s byte rate for STS-1 operation. This Bus permits the E1Mx16 to connect directly to other TranSwitch devices in application designs. The E1 signals can be either HDB3 positive/negative rail or NRZ format. The E1Mx16 provides performance counters, alarm detection, and the ability to generate errors and Alarm Indication Signals (AIS). E1 facility and line loopback capabilities are also provided.
APPLICATIONS
* STM-1/STS-3/STS-1 to 2.048 Mbit/s add/drop mux/demux * Unidirectional or bidirectional ring applications * STM-1/STS-3/STS-1 termination terminal mode multiplexer * STM-1/STS-3/STS-1 test equipment
PRELIMINARY information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product.
STM-1/STS-3/STS-1 TELECOM BUS SIDE
External Clock +5V
13 14 13 14
* * * * * * * * * * * * * *
2.048 Mbit/s TRIBUTARY SIDE
7
A - side drop bus A - side add bus B - side drop bus B - side add bus
Channel 1
P & N data and clock for receive and transmit, plus receive data zero-output control
E1Mx16 E1 Mapper 16-Channel TXC-04216
5 Boundary Scan 3 Microprocessor Controls interface
7
Channel 16
U.S. Patents No. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 U.S. and/or foreign patents issued or pending Copyright 2000 TranSwitch Corporation E1Mx16 is a trademark of TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number: PRELIMINARY TXC-04216-MB Ed. 2, October 2000
TranSwitch Corporation * 3 Enterprise Drive * Shelton, Connecticut 06484 Tel: 203-929-8810 * Fax: 203-926-9453 * www.transwitch.com
*
USA
DATA SHEET TABLE OF CONTENTS
E1Mx16 TXC-04216
SECTION PAGE List of Figures ...................................................................................................................3 Overview ............................................................................................................................4 Features .............................................................................................................................5 Block Diagram ..................................................................................................................10 Block Diagram Description ...............................................................................................11 Lead Diagram ..................................................................................................................15 Lead Descriptions ............................................................................................................16 Absolute Maximum Ratings and Environmental Limitations ............................................25 Thermal Characteristics ...................................................................................................25 Power Requirements .......................................................................................................25 Input, Output and Input/Output Parameters .....................................................................26 Timing Characteristics .....................................................................................................29 Operation ................................................................................................................... 44-87 Bus Interface Modes .............................................................................................. 44 Bus Mode Selection ............................................................................................... 45 SDH/SONET Add/Drop Multiplexing Format Selections ........................................ 45 Drop TU/VT Selection ............................................................................................ 46 Add TU/VT Selection ............................................................................................. 47 Bus Timing ............................................................................................................. 48 Unequipped Operation ........................................................................................... 48 Drop Bus Multiframe Alignment ............................................................................. 50 Add Bus Multiframe Alignment .............................................................................. 51 Performance Counters ........................................................................................... 52 Alarm Structure ...................................................................................................... 52 Interrupt Structure .................................................................................................. 53 SDH/SONET AIS Detection ................................................................................... 59 TU/VT Pointer Tracking ......................................................................................... 59 Remote Defect Indications ..................................................................................... 62 Overhead Communications Bit Access ................................................................. 66 J2 Byte Processing ................................................................................................ 67 N2 (Z6) Byte Processing (Tandem Connection) .................................................... 71 TUG-3 Null Pointer Indicator .................................................................................. 72 E1 Loopback Capability ......................................................................................... 73 PRBS Pattern Generator and Analyzer ................................................................. 74 Resets .................................................................................................................... 74 Start-Up Procedure ................................................................................................ 75 Pointer Leak Rate Calculations ............................................................................. 76 Jitter Measurements ................................................................................................77 Internal SPOT Processors ..................................................................................... 82 Boundary Scan ...................................................................................................... 86 Multiplex Format and Mapping Information ........................................................... 88 Memory Map ....................................................................................................................94 Memory Map Descriptions ..................................................................................... 100-133 Common Registers .............................................................................................. 100
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DATA SHEET
E1Mx16 TXC-04216
Port n Registers.....................................................................................................114 Application Examples ....................................................................................................134 Package Information ......................................................................................................135 Ordering Information ......................................................................................................136 Related Products ...........................................................................................................136 Standards Documentation Sources ...............................................................................137 List of Data Sheet Changes .......................................................................................... 139 Documentation Update Registration Form* ..............................................................143
* Please note that TranSwitch provides documentation for all of its products. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Page
TXC-04216 Block Diagram ......................................................................................10 2048 kbit/s Asynchronous Mapping .........................................................................13 E1Mx16 TXC-04216 Lead Diagram .........................................................................15 Groups 1-4, Ports 1-4 E1 Transmit Timing ...............................................................29 Groups 1-4, Ports 1-4 E1 Receive Timing ...............................................................30 STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus ...................31 STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus .......32 STS-1 A/B Add Bus Signals, Timing Derived from Add Bus ....................................33 STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus ........................34 Microprocessor Read Cycle Timing - Intel ...............................................................35 Microprocessor Write Cycle Timing - Intel ...............................................................37 Microprocessor Read Cycle Timing - Motorola .......................................................39 Microprocessor Write Cycle Timing - Motorola ........................................................41 Boundary Scan Timing ............................................................................................43 H4 Byte Floating VT Mode Bit Allocation .................................................................50 TU/VT Pointer Tracking State Machine ....................................................................61 Facility and Line Loopbacks .....................................................................................73 Jitter Tolerance and Jitter Test Arrangements ..........................................................78 Jitter Tolerance Measurements with Requirement ...................................................78 Jitter Transfer Measurements ...................................................................................79 Standard Pointer Test Sequences ............................................................................81 Schematic Diagram of E1Mx16 Showing SPOT Processor Interfaces ....................84 Recommended Implementation Flowchart for Reprogramming the SPOT Processor 85 Boundary Scan Schematic ......................................................................................87 Typical Application using the E1Mx16 ....................................................................134 E1Mx16 TXC-04216 388-Lead Plastic Ball Grid Array Package ............................135
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DATA SHEET OVERVIEW
E1Mx16 TXC-04216
The E1Mx16 (TXC-04216) provides the mapping of sixteen 2048 kbit/s E1 asynchronous signals into a multiple-segment, byte-parallel, SDH/SONET Telecom Bus for the STM-1, STS-3, or AU-3/STS-1 formats, using sixteen programmed asynchronous mode TU12/VT2 tributary signals. The E1Mx16 interfaces on the SDH/SONET side use four bus segments defined as A-side Drop and Add, and B-side Drop and Add. Selected TU-12/VT2 tributaries are mapped to and from either a 270 or 90 SDH/SONET column format. Using a dual bus architecture, the E1Mx16 can be configured in a system for dropping a TU-12/VT2 from either bus only, adding a TU-12/VT2 to either bus only, dropping and adding a TU-12/VT2 to either the A or B sides, dropping a TU-12/VT2 from either the A or B sides, and adding the TU-12/VT2 to the opposite bus (e.g. drop from A, add to B), or dropping a TU-12/VT2 from either A or B buses and adding the TU-12/VT2 to both buses. Bus timing for the Add side can be derived from either the Drop bus, or input signals to the Add bus. Each drop has an optional H4 byte detector for detecting the starting location of the V1 byte in the TU-12/VT2. Instead of using the H4 detector, a V1 pulse may be inputted to the E1Mx16. Each Drop bus is also equipped with an optional H1/H2 or the E1 bytes AIS detector for detecting an upstream AIS state. Each of the selected TU-12/VT2 for both the A and/or B drop buses has a pointer tracking state machine for determining the location of the overhead bytes and the E1 asynchronous frame bits. Each of the overhead bytes in the selected TU-12/ VT2 is monitored for control and status information. The E1Mx16 can be configured to perform a J2 16- byte trail trace message comparison, N2 tandem connection message comparison and generation with error counters and status alarm indications, V5 single-bit or enhanced 3-bit RDI, REI, signal label mismatch and unequipped detection and generation, and K4 byte access. The E1Mx16 provides a desynchronizer/synchronizer for each port. An 8-bit pointer leak rate register is provided. The E1Mx16 satisfies the various jitter tolerance, jitter transfer, mapping jitter, and combined jitter requirements found in ITU and ANSI documents. Each of the asynchronous E1 line inputs can be individually configured to provide either an NRZ interface or a dual unipolar rail type interface. When configured for a rail interface, a B3ZS CODEC converts the rail signals to and from a NRZ signal. Coding violations are counted in a 16-bit counter. For overhead byte processing, the E1Mx16 uses an internal SPOT (SDH/SONET Processor for Overhead Termination). The SPOT is divided into four segments corresponding to the four groups of four mappers. The SPOT performs many of the overhead processing functions, such as J2 message comparisons. Programming of the SPOT is performed through the microprocessor bus. The microprocessor can access four separate segments of the SPOT which have individual select leads, corresponding to the four groups of four mappers. SELp (p = 1 to 4) are the microprocessor port select signals. SEL1 selects the first group of four mappers (channels 1-4) and SEL2, SEL3 and SEL4 select the other three groups of four mappers. The E1Mx16 is compatible with either Intel or Motorola split bus microprocessors. The E1Mx16 also provides interrupts to the microprocessor for operational alarm status indications.
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DATA SHEET FEATURES
The following features are supported by the E1Mx16: SDH/SONET FORMATS: * STM-1 AU-4 VC-4 TUG-3 TUG-2 format * STM-1 AU-3 TUG-2 * STS-3 * STS-1 OPERATING MODES:
E1Mx16 TXC-04216
The E1Mx16 supports the following modes of operation which are programmable by the microprocessor. * Drop mode only (Add bus tristated) - Drop from A or B * Add mode only - Add to A or B * Single unidirectional ring - Drop from A, Add to A - Drop from B, Add to B * Multiplexer - Drop from A, Add to B - Drop from B, Add to A * Dual protection ring - Drop from A, Add to A and B - Drop from B, Add to A and B
BUS TIMING: The E1Mx16 provides the following bus timing modes by lead selection with software overwrite: * Drop bus timing - Add bus timing is derived from the same named Drop bus * Add bus timing - Add bus timing is independent of the Drop bus SDH/SONET BUS INTERFACE: * STM-1/STS-3 - 19.44 Mbyte/s parallel interface * STS-1 - 6.48 Mbyte/s parallel interface
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DATA SHEET
* Drop bus timing enabled - Drop bus inputs: Clock, SPE, C1J1V1, Data and parity - Add bus outputs: data, parity and active bus indication * Add bus timing enabled - Drop bus inputs: Clock, SPE, C1J1V1, data, parity and bus indication - Add bus inputs: Clock, SPE and C1J1V1 - Add bus outputs: Data, parity and active bus active indication * Stuck clock indications - Input parity check with alarm monitoring Odd, even, data only, or all bus signals - Input loss of clock detection Stuck high or low * SDH/SONET interface Add buses, A and B - Output parity generation Odd, even, data only, or all bus signals - Bus indication (polarity selectable through control bit) - Ability to High-Z the output bus signals
E1Mx16 TXC-04216
MAPPINGS: The E1Mx16 has the following mapping features: * Maximum of 16 E1 ports - Up to 16 E1 asynchronous mappings to TU-12/VT2 * TU-12/VT2 selection - Drop bus (common A and B sides) - Add bus (common A and B sides) * User's responsibility to maintain TUG-2/VT group mappings SDH/SONET FEATURES: * In-band upstream path and line AIS detection - H1/H2 pointer bits or - E1 bytes (majority vote) * TU/VT pointer tracking for A and B sides - ETSI 1015-based state machine - Size error indication - 4-bit increment/decrement counters * TU/VT A/B Drop and Add selection * TU/VT pointer generation - Fixed to 105 for 2048 kbit/s E1 asynchronous format
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DATA SHEET
* Low order TU/VT byte processing - J2 byte (programmable per port) 64-byte host processor read cycle (no alignment) 16-byte host processor read with ITU TTC message comparison - V5 byte and K4 (Z7) byte Single-bit RDI or enhanced 3-bit RDI alarm detection (5 or 10 event option, selectable through software control bit) REI (FEBE) counter (8 bits) BIP-2 detector and counter (8 bits) with block or bit error count Detect RFI (bit 4 in V5 byte) Signal label mismatch, unequipped detection, Access to K4 byte - N2 (Z6) byte Host processor access or Tandem connection option with: Multiframe pattern alignment 16-byte message comparison TC RDI, ODI alarm detection REI and OEI counters - V4 byte access - Line AIS generation on SDH/SONET alarms with: Masks Microprocessor control * Low order TU/VT byte insertion - J2 byte with 16- or 64-byte message - V5 and K4 (Z7) byte with: REI (FEBE) insertion (from receive side) RFI insertion (microprocessor control) BIP-2 calculation and insertion RDI insertion (from receive side) with: Enable bits for alarms Microprocessor control
E1Mx16 TXC-04216
Single-bit RDI or enhanced 3-bit RDI (selectable through software control bit) Control of spare bits in K4 byte - N2 (Z6) byte Microprocessor or Tandem connection insertion with: Multiframe pattern generation 16-byte message TC RDI, ODI generation with: Alarms and microprocessor control
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DATA SHEET
TC AIS, REI and OEI generation - Unequipped channel generation with supervisory equipped generation - TU/VT AIS generator * Desynchronizer - Meet ETSI and ANSI performance requirements for: Pointer test sequence Jitter - External clock (also used for line AIS generation) * O-bit channel microprocessor access - For selected TU-12/VT2
E1Mx16 TXC-04216
LINE INTERFACE: * Individual port NRZ or rail interface selection * NRZ interface - AIS detection - External loss of signal may be inputted on negative rail - Programmable clock edge * Rail Interface - HDB3 CODEC - Bipolar violation counter (16 bits) - Loss of signal detection - AIS detection * Quiet feature - Force receive output to 0 * High-Z feature
TEST FEATURES: * Boundary Scan based on IEEE 1149.1 - EXTEST, SAMPLE, BYPASS test instructions * Loopbacks per port - Facility - Line * High-Z all output leads option * BIP-2 error mask per port - Force inverted value continuous * REI error mask per port - Force REI to be sent as a 1 * Pseudo-random test generator and analyzer per port - 215-1 pattern defined in O.151
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DATA SHEET
MICROPROCESSOR INTERFACE: * Split bus - Intel - Motorola * Interrupt support - Positive, negative, or positive/negative alarm transition - Positive level option - Software polling registers - Mask bit alarm hierarchy - Hardware enable control bit - Hardware sense control * Reset control bits - Hardware reset - Full software reset - Software reset for A and B bus alarms - Software reset per port - Counter reset per port - SPOT (internal processor) reset SPOT PROCESSOR: * Microcode is supplied for initialization * Downloaded through memory map * Sanity alarms
E1Mx16 TXC-04216
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DATA SHEET BLOCK DIAGRAM
STM-1/STS-3/STS-1 TELECOM BUS SIDE
E1Mx16 TXC-04216
2.048 Mbit/s TRIBUTARY SIDE
EXTCK ADCLK ADSPE ADC1J1V1 AD(7-0) 8 ADPAR ADINDp 4 12 Repeated for Ports 1 through 16 A Receive (A Drop) TU/VT Terminate A Side Destuff Desync HDB3 Coder QUIETpn RPOpn RNOpn RCOpn
Add/Drop Bus A Interface to Channel blocks #1-16
B Receive (B Drop)
TU/VT Terminate B Side
AACLK AASPE AAC1J1V1 AA(7-0) 8 AAPAR AADDp 4 4 AAINDp 3 11
SPOT RISC Processor and RAM
Alarms & Controls
Alarms Controls, & Timing A Transmit (A Add) TU/VT Build A Side Stuff/Sync A Side HDB3 Decoder B Transmit (B Add) TU/VT Build B Side Stuff/Sync B Side Repeated for Ports 1 through 16 12 TPIpn TNIpn/TLOSpn TCIpn
BDCLK BDSPE BDC1J1V1 BD(7-0) 8 BDPAR BDINDp 4
Note: p=1-4; n=1-4 (16 Channel blocks)
TCK TDO TRS TDI TMS Test Access Port Interface (Boundary Scan)
Add/Drop Bus B Interface to Channel blocks #1-16
Channel 1 2 3 4 5 6 7 8
p 1 1 1 1 2 2 2 2
n 1 2 3 4 1 2 3 4
Channel 9 10 11 12 13 14 15 16
p 3 3 3 3 4 4 4 4
n 1 2 3 4 1 2 3 4
4 1
T A P
BACLK BASPE BAC1J1V1 BA(7-0) 8 BAPAR BADDp 4 4 BAINDp
RESET
3 11
HIGHZ ABUST TESTp TESTp TXCTI(1-5)
Microprocessor Interface and Common Control/Status I/O
Note: p=1-4 (for four groups of four mappers)
4
8
11
4
4
SELp MOTO RD/WR
LDS INTSH
D (7-0)
DTACKp A (10-0)
IRQp
MOTOROLA
4
8
11
4
4
SELp MOTO RD
WR INTSH
D (7-0) A (10-0)
RDYp
INTp
INTEL
Figure 1. TXC-04216 Block Diagram
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DATA SHEET BLOCK DIAGRAM DESCRIPTION
E1Mx16 TXC-04216
The block diagram for the E1 Mapper 16-Channel device is shown in Figure 1. The E1Mx16 interfaces to four buses, designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STM-1/STS-3 rate of 19.44 Mbyte/s, or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous E1 signals are carried in floating Virtual Tributary 2 (VT2) format in a Synchronous Transport Signal - 1 (STS-1), or in an STS-1 that is carried in a Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the E1 signals are carried in floating mode Tributary Unit - 12 (TU-12) format in the STM-1 Virtual Container - 4 structure (VC-4) using Tributary Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary Unit Group - 2 (TUG-2) mapping schemes. Sixteen E1 signals can be dropped from one bus (A Drop or B Drop), or from any combination of the two drop buses, to the E1 lines. Sixteen asynchronous E1 signals are converted into TU-12 or VT2 format and are added to either one or both of the add buses, depending upon the mode of operation. When the E1Mx16 is configured for drop bus timing, the add buses are, by definition, bytesynchronous and multiframe-synchronous with their like-named drop buses, but are delayed by one byte time because of internal processing. For example, if a byte in the STM-1 Virtual Container - 4 structure (VC-4) using a Tributary Unit Group - 3 (TUG-3) TU-12/VT2 is to be added to the A Add bus, the time of its placement on the bus is derived from the A Drop bus timing, and from software instructions specifying which TU/VT number is being dropped/added. When the device is configured for add bus timing, the add bus, parity, and add indicator signals are derived from the add clock, C1J1V1 and SPE signals. The A Receive block is identical to the B Receive block. The TU/VT Terminate block is repeated 32 times, two for each port (A and B sides). The Destuff, Desync, and HDB3 Coder blocks are repeated sixteen times, one for each port. The interface between a drop bus and Receive block consists of 12 input leads, and an optional output lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication making the signal a C1J1V1 indicator, an SPE indicator, and an odd parity lead for the last-named ten leads. Parity is selectable by control bits for even parity and for the data byte only. The output lead is an optional TU/VT select indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine the location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is low. A single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is high. Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in each of the STS-1 signals. The E1Mx16 can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector for determining the location of the V1 pulse. The V1 pulse location is used to determine the location of the pointer byte V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur during three drop bus clock cycles every four frames following the J1 pulse when the SPE signal is high. For STS-3 operation, three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three clock cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte location is six clock cycles after the V1 pulse. For STS-1 operation, one V1 pulse must be present if the C1J1V1 signal is used. The V1 pulse must occur on the next clock cycle after the J1 pulse, and when the SPE signal is high. The J1 pulse identifies the J1 byte location (defined as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle) the TUs start. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the V1 bytes for the 21 TU-12/VT2s are also aligned with respect to the V1 pulse. Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream SDH/SONET AIS indication. The E1Mx16 can monitor either the TOH E1 bytes or the H1/H2 bytes for an AIS indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected.
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DATA SHEET
E1Mx16 TXC-04216
Each TU/VT Terminate block (A and B side) performs pointer processing based on the location of the V1 and V2 bytes. The pointer bytes are monitored for loss of pointer, TU AIS indication, and NDF. The pointer tracking process is based on the latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer increments and decrements are also counted, and the SS-bits are monitored for the correct value. This block also monitors the various alarms found in the V5 and K4 (formerly known as Z7) bytes, including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection and error counter, REI counter, and the three RDI indications. The E1Mx16 performs a 16-byte J2 trail trace comparison on the channels selected. For 64-byte messages, the bytes are stored in a memory map segment for a microprocessor read cycle. The device also provides the TU tandem connection feature and performs the 16-byte message comparison for the N2 (formerly known as Z6) byte message. A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in the Destuff block using majority logic rules for the three sets of three justification control bits to determine if the two S-bits are data bits or frequency justification bits. The Desync block removes the effects on the E1 output of systemic jitter that might occur because of signal mappings and pointer movements in the network. The Desync block contains two parts, a pointer leak buffer, and an E1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can adjust the effect over time. The E1 Loop Buffer consists of a digital loop filter, which is designed to track the frequency of the received E1 signal and to remove both transmission and stuffing jitter. An option for each port provides either NRZ data, or an HDB3-encoded positive and negative rail signal for the E1 interface. Receive data (towards the E1 line), for all sixteen channels, can be clocked out on either rising or falling edges of the clock. In addition, control bits are provided for forcing the data and clock signals to a high impedance state (tri-state). A control lead is provided for forcing the output leads to the 0 state. In the add direction, the E1Mx16 accepts clock and either NRZ data or HDB3-encoded positive and negative rail signals. Data, for all sixteen channels, can be clocked in on either the falling or rising edge of the clock. In the NRZ mode, an external loss of clock indication input signal can be provided. For the rail signal, coding violations are counted, and there is monitoring for loss of signal. An E1AIS detector is also provided. The data signal is written into a FIFO in one of the 32 Stuff/Sync blocks. Threshold modulation is used for the frequency justification process. Timing information from the drop bus or add bus is used to read the FIFO and perform the TU/VT justification process. This block permits tracking of an incoming E1 signal having an average frequency offset as high as 120 ppm, and up to 1.5 UI of peak-to-peak jitter. Since the E1Mx16 supports a ring architecture, two sets of blocks are provided for each port. The TU/VT selection is the same for both blocks. A control bit, and transmit line alarms, can generate an E1AIS. The 32 TU/VT Build blocks format the TU/VT into a STS-1, STS-3 or STM-1 structure for the asynchronous 2048 kbit/s signals, as shown in Figure 2. The pointer value carried in the V1 and V2 bytes is transmitted with a fixed value of 105. Transmit access is provided for the 8 overhead communications channel bits (O-bits) via the microprocessor. The microprocessor also writes the signal label, and the value of the J2 message, either as a 16-byte or a 64-byte message. The E1Mx16 provides the TU tandem connection feature for the TU, including the transmission of the 16-byte message and the various alarms associated with the tandem connection feature. The device provides single-bit or 3-bit RDI using the V5 and K4 (Z7) bytes, respectively. Local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. The Far End Block Error FEBE (REI) is inserted from the BIP-2 errors detected on the receive side, and BIP-2 parity is generated for the V5 byte. Control bits are provided for generating unequipped status, generating TU/VT AIS, and inserting REI and BIP-2 errors. The ability to generate Null Pointer Indicators (NPIs) is also provided for the STM-1 VC-4 format.
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DATA SHEET
E1Mx16 TXC-04216
Figure 2. 2048 kbit/s Asynchronous Mapping
VC-12 V5 RRRRRRRR 32 bytes (2048 kbit/s Data) RRRRRRRR J2 C1 C2 O O O O R R 32 bytes (2048 kbit/s Data) RRRRRRRR N2 (Z6) C1 C2 O O O O R R 32 bytes (2048 kbit/s Data) RRRRRRRR K4 (Z7) C1 C2 R R R R R S1 S2 I I I I I I I 31 bytes (2048 kbit/s Data) RRRRRRRR 140 Bytes Path Overhead (V5) Byte BIP-2 1 BIT 1 BIP-2 = Bit Interleaved Parity (2 bits) REI = Remote Error Indication (formerly FEBE, Far End Block Error Indication) RFI = Remote Failure Indication L1L2L3 = Signal Label RDI = Remote Defect Indication (formerly FERF, Far End Receive Failure Indication) V1 REI
(FEBE)
TU-12/VT2 V1 (Pointer Byte)
35 bytes
V2 (Pointer Byte)
35 bytes
V3 (Action)
I = Information O = Overhead communications Ct = Justification control Sq = Justification opportunity R = Fixed stuff (set to 0)
35 bytes
V4 (Reserved)
500 s
35 bytes
144 Bytes RDI
(FERF)
RFI
L1
L2 L3 Signal Label
8 V2
NDF
S1 S2 I
D
I
D
I
D
I
D
I
D
New Data Flag Normal = 0110, 1110, 0010, 0100 or 0111 New = 1001, 0001, 1101, 1011 or 1000 Positive Justification = Invert five I-bits Negative Justification = Invert five D-bits Pointer Range = 0 - 139 decimal
Size S1S2 = 10
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
The A Transmit block is identical to the B Transmit block. The interface between an add bus and a Transmit block consists of three input leads and eleven output leads, when the add bus timing mode is selected. The input leads are a byte clock, a C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, a parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The Add C1J1V1 signal is used in conjunction with the Add SPE signal to determine the location of the various pulses. An option is provided in which the drop side V1 reference pulse, either from the drop bus C1J1V1 indicator or from the H4 multiframe detector, may be used as the add side V1 reference pulse. When drop bus timing is selected, the output leads are byte-wide data, a parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The add bus clock, SPE and C1J1V1 signals are disabled. The E1Mx16 can be configured to operate with either Intel or Motorola-compatible microprocessors via the Microprocessor Interface blocks. Separate address, data and control leads are provided. The microprocessor can access four separate segments of memory which have individual select, ready/acknowledge and interrupt leads, corresponding to the four groups of four mappers. Interrupt capability is provided with mapper group and individual mapper mask bits as well as activity registers to guide software to the exact cause of an interrupt in the most expeditious manner. A wide variety of alarms is provided on a mapper group level as well as on a per mapper channel level. Each alarm or error is reflected in a current status register or counter as well as a latched value register that may be set on the rising, falling, both transitions or positive level of an alarm. Any latched value may trigger an interrupt, unless it is masked to prevent it causing an interrupt. An option is provided which permits the interrupt polarity to be inverted. Control bits are provided which enable an E1 facility or line loopback. Because of the complexity of the SDH/ SONET interface and the two timing modes, SDH/SONET loopback of the TU/VTs is not supported. The SPOT (SONET Processor for Overhead Termination) block is a RISC processor with associated instruction and data memory that performs selected low-speed functions, including all overhead processing and counter maintenance. The SPOT program must be loaded into the SPOT instruction memory after power-up. Executable microcode is provided by TranSwitch. All four SPOT blocks can be programmed at the same time by simultaneously activating all four SELp leads in write mode. The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external I/O leads from the TAP for board and component test.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET LEAD DIAGRAM
E1Mx16 TXC-04216
51
58
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26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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AE AF AD
AC AB
AA
YW V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Notes: This is the bottom view. The leads are solder balls. See Figure 26 for package information.
Figure 3. E1Mx16 TXC-04216 Lead Diagram
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET LEAD DESCRIPTIONS
E1Mx16 TXC-04216
In the following tables the mapper-group identification variable "p" stands for "(1-4)", and the corresponding leads are listed in the order 1, 2, 3, 4. POWER SUPPLY, GROUND AND NO CONNECT Symbol VDD Lead No. A2, A14, B26, C23, D3, L12, L13, L14, L15, M11, M16, N1, N11, N16, P11, P16, P26, R11, R16, T12, T13, T14, T15, AC24, AD4, AE1, AF13, AF25 A1, A13, A26, D4, D21, D22, D23, E4, F4, L11, L16, M12, M13, M14, M15, N12, N13, N14, N15, N26, P1, P12, P13, P14, P15 R12, R13, R14, R15, T11, T16, AA23, AB23, AC4, AC5, AC6, AC23, AF1, AF14, AF26 I/O/P * Type P Name/Function VDD: +5 volt supply voltage, 5%.
GND
P
Ground: 0 volt reference.
Note: I = Input; O = Output; P = Power; T=Tristate
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol NC
Lead No. B7, C6, C7, C8, C17, C19, C20, D5, D6, D7, D17, D19, D20, E2, E3, F24, G24, J1, J2, K1, K2, K4, K23, L1, L3, L23, M3, M4, M23, M24, N3, N4, P2, P3, P23, R3, T2, T3, T23, U3, U4, U23, V3, V4, V23, V24, V25, W23, W24, Y23, Y24, Y25, AA24, AA25, AB4, AB24, AB25, AB26, AC1, AC2, AC13, AC14, AC15, AC21, AC22, AD1, AD5, AD6, AD13, AD14, AD21, AD23, AD24, AE6, AE21, AE24, AE25, AE26, AF2
I/O/P * Type
No Connect: NC leads are not to be connected, not even to another NC lead, but must be left floating. Connection of these leads may impair performance or cause damage to the device.
A DROP AND A ADD BUS I/O (p=1-4) Symbol ADCLK Lead No. I/O/P Type * R2 I TTL Name/Function A Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/ STS-3 operation, and at 6.48 MHz for STS-1 operation. A Drop bus byte-wide data (AD7-AD0), the parity bit (ADPAR), SPE indication (ADSPE), and the C1J1V1 indication (ADC1J1V1) are clocked in on falling edges of this clock. This clock may also be used for timing and deriving the like-named add bus byte-wide data, add and TU/VT indications, and parity bits. The add bus signals are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. A Drop Bus Parity Bit: An odd parity bit input signal representing the parity calculation for each data byte, SPE, and C1J1V1 signal from the drop bus. Control bits are provided in address 012H which enable parity to be calculated as even (control bit DPEp is 1), and/or for the data byte only (control bit PDDOp is 1).
ADPAR
AF15
I
TTL
*See Input, Output and Input/Output Parameters section below for Type definitions.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol AD(7-0)
Lead No. I/O/P Type * AF3, AE3, AE4, AF4, AE5, AE18, AF17, AF18 AC3 I TTL
A Drop Bus Data Byte: Byte-wide data that corresponds to the STM-1/STS-3/STS-1 signal from the drop bus. The first bit received (dropped) corresponds to bit 7.
ADSPE
I
TTL
A Drop Bus SPE Indicator: A signal that is active high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead times. A Drop Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the ADSPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when ADSPE is low. The J1 signal identifies the starting location of the J1 signal when ADSPE is high. One or more V1 pulses may be present depending upon the format. The V1 pulses may be used in place of the H4 byte as the multiframe indication.
ADC1J1V1
AB2
I
TTL
ADINDp
G3, K3, AA2, AD16 N2
O
CMOS A Drop Bus TU/VT Selection Indication: Enabled when control bit 4mA ADnENp is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (RTUNnp register) for each port (n=port number, 1-4; p=group number, 1-4). TTL A Add Bus Clock: When the add bus timing mode is selected, this input must be provided for add bus timing. This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. The add bus SPE indication (AASPE), and the C1J1V1 indication (AAC1J1V1) are clocked in on falling edges of this clock. Add bus bytewide data (AA7-AA0), add indicator (AADDp), and parity bit (AAPAR) are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. When drop bus timing is selected, this input is disabled.
AACLK
I
AAPAR
AF19
O(T) CMOS A Add Bus Parity Bit: An odd parity output signal that is calculated 4mA over the byte-wide add data. This tristate lead is only active when there is data being added to the add bus. When control bit APEp is 1, even parity is calculated.
AA(7-0)
O(T) CMOS A Add Bus Data Byte: Byte-wide data that corresponds to the AF21, 4mA selected TU/VT. AF20, AF6, AE7, AF7, AD7, AC7, AE8 M1 I TTL A Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead byte times.
AASPE
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol AAC1J1V1
Lead No. I/O/P Type * AB1 I TTL
A Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the AASPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when AASPE is low. The J1 signal identifies the starting location of the J1 signal when AASPE is high. The J1 signal identifies the location of the J1 byte. One or more V1 pulses may be present depending upon the format. The V1 pulses are used in place of the H4 byte as the multiframe indication.
AAINDp
H2, J3, AA3, AC16 R4, AD26, AF5, AE19
O
CMOS A Add Bus TU/VT Selection Indication: Enabled when control bit 4mA AAnENp is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (TTUNnp register) for each port (n=port number, 1-4; p=group number, 1-4). CMOS A Add Bus Add Data Present Indicator: This normally active low sig4mA nal is present when output data to the A Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDIp is 1, the indicator is active high instead of active low.
AADDp
O
B DROP AND B ADD BUS I/O (p=1-4) Symbol BDCLK Lead No. I/O/P Type P25 I TTL Name/Function B Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/ STS-3 operation, and at 6.48 MHz for STS-1 operation. B Drop bus byte-wide data (BD7-BD0), the parity bit (BDPAR), SPE indication (BDSPE), and the C1J1V1 indication (BDC1J1V1) are clocked in on falling edges of this clock. This clock may also be used for timing and deriving the like-named add bus byte-wide data, add and TU/VT indications, and parity bits. The add bus signals are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. B Drop Bus Parity Bit: An odd parity bit input signal representing the parity calculation for each data byte, SPE, and C1J1V1 signal from the drop bus. Control bits are provided in address 012H which enable parity to be calculated as even (control bit DPEp is 1), and/or for the data byte only (control bit PDDOp is 1). B Drop Bus Data Byte: Byte-wide data that corresponds to the STM-1/STS-3/STS-1 signal from the drop bus. The first bit received (dropped) corresponds to bit 7. B Drop Bus SPE Indicator: A signal that is active high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead times.
BDPAR
J23
I
TTL
BD(7-0)
J26, J25, J24, K26, K25, K24, L26, L25 H24
I
TTL
BDSPE
I
TTL
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol BDC1J1V1
Lead No. I/O/P Type H25 I TTL
B Drop Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the BDSPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when BDSPE is low. The J1 signal identifies the starting location of the J1 signal when BDSPE is high. One or more V1 pulses may be present depending upon the format. The V1 pulses may be used in place of the H4 byte as the multiframe indication.
BDINDp
L24, G26, AA26, Y26 M25
O
CMOS B Drop Bus TU/VT Selection Indication: Enabled when control bit 4mA BDnENp is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (RTUNnp register) for each port (n=port number, 1-4; p=group number, 1-4). TTL B Add Bus Clock: When the add bus timing mode is selected, this input must be provided for add bus timing. This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. The add bus SPE indication (BASPE), and the C1J1V1 indication (BAC1J1V1) are clocked in on falling edges of this clock. Add bus bytewide data (BA7-BA0), add indicator (BADDp), and parity bit (BAPAR) are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. When drop bus timing is selected, this input is disabled.
BACLK
I
BAPAR
AD25
O(T) CMOS B Add Bus Parity Bit: An odd parity output signal that is calculated 4mA over the byte-wide add data. This tristate lead is only active when there is data being added to the add bus. When control bit APEp is 1, even parity is calculated.
BA(7-0)
O(T) CMOS B Add Bus Data Byte: Byte-wide data that corresponds to the AE23, 4mA selected TU/VT. AF23, AE22, AF22, AD22, AF10, AF9, AF8 AC26 I TTL B Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead byte times. B Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the BASPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/ STS-3 signal, and the C1 byte in the STS-1 signal, when BASPE is low. The J1 signal identifies the starting location of the J1 signal when BASPE is high. The J1 signal identifies the location of the J1 byte. One or more V1 pulses may be present depending upon the format. The V1 pulses are used in place of the H4 byte as the multiframe indication.
BASPE
BAC1J1V1
H26
I
TTL
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol BAINDp
Lead No. I/O/P Type F23, G25, AF12, W26 AC25, M26, AF11, AF24 O
CMOS B Add Bus TU/VT Selection Indication: Enabled when control bit 4mA BAnENp is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (TTUNnp register) for each port (n=port number, 1-4; p=group number, 1-4). CMOS B Add Bus Add Data Present Indicator: This normally active low sig4mA nal is present when output data to the B Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDIp is 1, the indicator is active high instead of active low.
BADDp
O
GROUP p, PORT n LINE INTERFACE (p = 1-4; n = 1-4) Symbol RCOpn Lead No. I/O/P Type Name/Function
F3, B11, D1, O(T) CMOS Receive Group p, Port n Output Clock: A 2.048 MHz clock output. 4mA Data is normally clocked out on rising edges of this clock. When conA16, D16, trol bit RCLKIp is 1, data is clocked out on falling edges of this clock. D26, D12, When control bit RnENp is 0, this lead is forced to a high impedance C22, W2, state. AC9, W1, Note: RCO11 is lead F3, RCO12 is lead B11, RCO13 is lead D1, AD9, AD18, RCO14 is lead A16, RCO21 is lead D16, etc. U25, AE9, T25 F1, C11, E1, B10, B16, E23, C15, D24, Y4, AE10, W3, AC8, AC12, T26, AC18, R26 O(T) CMOS Receive Group p, Port n Data Positive Rail or NRZ: When control 4mA bit BYPASnp is 0, positive rail data is provided on this lead. When control bit BYPASnp is 1, an NRZ signal is provided on this lead. When control bit RnENp is 0, this lead is forced to a high impedance state. Note: RPO11 is lead F1, RPO12 is lead C11, RPO13 is lead E1, RPO14 is lead B10, RPO21 is lead B16, etc.
RPOpn
RNOpn
F2, D9, D2, O(T) CMOS Receive Group p, Port n Data Negative Rail: When control bit 4mA BYPASnp is 0, negative rail data is provided on this lead. When conB8, C16, E25, trol bit RnENp is 0, or control bit BYPASnp is 1, this lead is forced to D13, D25, Y1, a high impedance state. AD17, W4, Note: RNO11 is lead F2, RNO12 is lead D9, RNO13 is lead D2, AD8, AC17, RNO14 is lead B8, RNO21 is lead C16, etc. T24, AE17, R24 G1, C10, B2, B12, D8, E26, C14, C24, Y2, AD10, U1, AD11, AD15, U26, AC20, N25 H3, C9, C2, B14, D18, F26, H4, C26, AA4, AE12, V2, AD19, AF16, V26, AC19, R23 I TTL Transmit Group p, Port n Input Clock: A 2.048 MHz clock input. Data is normally clocked in on falling edges of this clock. When control bit TCLKIp is 1, data is clocked in on the rising edges of this clock. Note: TCI11 is lead G1, TCI12 is lead C10, TCI13 is lead B2, TCI14 is lead B12, TCI21 is lead D8, etc. Transmit Group p, Port n Data Positive Rail or NRZ: When control bit BYPASnp is 0, positive rail input data is provided on this lead. When control bit BYPASnp is 1, an NRZ signal is provided on this lead. Note: TPI11 is lead H3, TPI12 is lead C9, TPI13 is lead C2, TPI14 is lead B14, TPI21 is lead D18, etc.
TCIpn
TPIpn
I
TTL
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Name/Function
Symbol TNIpn/ TLOSpn
Lead No. H1, D10, C1, B13, C18, F25, B9, C25, AA1, AC11, V1, AD12, AE16, W25, AD20, N24
I/O/P Type I TTL
Transmit Group p, Port n Data Negative Rail/External Loss Of Signal: When control bit BYPASnp is 0, negative rail input data is provided on this lead. When control bit BYPASnp is 1, this lead may be used to input an active low external loss of signal indicator from the line interface device. Note: TNI11/TLOS11 is lead H1, TNI12/TLOS12 is lead D10, TNI13/ TLOS13 is lead C1, TNI14/TLOS14 is lead B13, TNI21/TLOS21 is lead C18, etc. Quiet Group p, Port n: A high forces the RPOpn and RNOpn leads to the 0 state for either a rail or NRZ interface, overriding control bit RnENp when it is 0. A low disables this feature. Note: QUIET11 is lead G2, QUIET12 is lead D11, QUIET13 is lead B1, QUIET14 is lead C12, QUIET21 is lead G4, etc.
QUIETpn G2, D11, B1, C12, G4, E24, B15, B24, Y3, AC10, U2, AE11, AE13, U24, AE20, N23
I
TTL
MICROPROCESSOR BUS INTERFACE SELECTION Symbol Lead No. I/O/P MOTO R1 I Type TTL Name/Function Motorola Mode: Intel bus interface is selected when low. Motorola bus interface is selected when high. This selection modifies some bus interface lead functions, as described in the next section of this table.
MICROPROCESSOR BUS INTERFACE - SPLIT BUS FOR MOTOROLA (M) OR INTEL (I) (p=1-4) Symbol Lead No. A(10-0) I/O/P Type Name/Function
I TTL Address Bus: These address line inputs are used for accessing an A15, C3, B3, A3, (Note 1) (Note 1) E1Mx16 memory location for a read/write cycle. A10 is the most significant bit. High is logic 1. A4, C5, B20, A7, A20, B21, A8 I/O TTL Data Bus: Bidirectional data lines used for transferring data to or D(7-0) C21, B22, 8mA from an E1Mx16 memory location. D7 is the most significant bit. A22, A9, High is logic 1. A23, B23, A24, A10 A6, A19, I TTL Select: A low enables data transfers between the microprocessor SELp P4, B18 and a group p address of the E1Mx16 memory during a read/write cycle. Only one SELp lead may be held low for a read cycle. D14 I TTL Read (I mode) or Read/Write (M mode): RD / Intel Mode - An active low signal generated by the microprocessor RD/WR for reading the E1Mx16 memory locations. Motorola Mode - An active high signal generated by the microprocessor for reading the E1Mx16 memory locations. An active low signal is used to write to memory locations.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Symbol Lead No. WR / LDS D15 I/O/P I Type TTL Name/Function
E1Mx16 TXC-04216
RDYp/ A11, A25, DTACKp A17, P24
O(T)
TTL 8mA
INTp / IRQp
B5, B17, J4, G23
O(T)
TTL 8mA
INTSH
A18
I
TTL
Write (I mode) or Device Select (M mode): Intel Mode - An active low signal generated by the microprocessor for writing to the E1Mx16 memory locations. Motorola Mode - The SELp and LDS inputs are logically OR-gated inside the E1Mx16, generating an internal active low select signal (CS) that is similar to SELp. This internal signal is used to enable data transfer. This lead can be used for the interface with the Motorola 68302 microprocessor. If it is not used, it should be tied to ground, so that CS is the same signal as SELp. Ready (I mode) or Data Transfer Acknowledge (M mode): Intel Mode - A high is an acknowledgment from the addressed group p E1Mx16 memory location that the transfer can be completed. A low indicates that the Mapper cannot complete the transfer cycle, and that microprocessor wait states must be generated for that group. Motorola Mode - During a read bus cycle, a low signal indicates that the information on the data bus is valid. During a write bus cycle, a low signal acknowledges the acceptance of data. This lead is tristated. Interrupt: When INTSH is high, a high on this output lead signals an interrupt request INTp to the microprocessor, as required for Intel. When INTSH is low, a low signals an interrupt request IRQp to the microprocessor, as required for Motorola. Interrupt Sense High: Interrupt polarity select. A high on this lead causes the interrupt sense to be high when an interrupt occurs. A low causes the interrupt sense to be low when an interrupt occurs. This lead must be set to meet the interrupt polarity requirement of the microprocessor.
Note 1: Leads A(10-0) are implemented as I/O type TTL 4mA to support production tests but are used as TTL inputs.
CONTROLS, EXTERNAL CLOCK AND TEST LEADS (p=1-4) Symbol Lead No. I/O/P Type TESTp A12, B25, M2, R25 TESTp TXCTI1 TXCTI2 TXCTI3 TXCTI4 TXCTI5 EXTCK B6, B19, T4, H23 A5, T1 L4, AD2, AE15 C13 I I I I Name/Function
CMOS TranSwitch Test Leads: A low must be placed on these leads. TTLp TranSwitch Test Leads: These leads are pulled high internally by an internal pull-up to VDD. They must be left floating or held high. TTL TranSwitch Test Leads: These leads must be tied low for proper operation. TTLp TranSwitch Test Leads: These leads are not to be connected, not even to another lead and must be left floating. Connection of these leads may impair performance or cause damage to the device. CMOS External Reference Clock: This clock is used for desynchronizer operation and other purposes. The clock frequency must be 58.32 MHz ( 30 ppm over life) and the clock duty cycle must be (50 10) %.
I
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Symbol Lead No. I/O/P Type RESET B4 I TTL Name/Function
E1Mx16 TXC-04216
HIGHZ ABUST
A21 C4
I I
TTL TTL
Hardware Reset: When an active low pulse is applied to this lead for a minimum duration of 150 nanoseconds after power is applied, this pulse clears all performance counters and alarms, resets the control bits (except those bits that force a high impedance state for the add buses), and initializes the internal FIFOs and internal SPOT processor. The microprocessor must write the control bit states for normal operation. High Impedance Select: A low forces all output leads to the high impedance state for testing purposes (except TDO). Add Bus Timing Select: A low selects the A and B Add bus clock, SPE and C1J1V1 input signals for deriving timing for the A and B Add buses. A high selects the like-named drop bus for deriving timing (e.g., A Drop bus for A Add bus). This control lead is disabled for group p when a 1 is written to control bit SBTENp. Control bit DRPBTp then makes the timing source selection for group p.
BOUNDARY SCAN INTERFACE SIGNALS Symbol Lead No. I/O/P Type TCK AE2 I TTL Name/Function IEEE 1149.1 Test Port Serial Scan Clock: This signal is used to shift data into TDI on the rising edge, and out of TDO on the falling edge. The maximum clock frequency is 10 MHz. IEEE 1149.1 Test Port Mode Select: TMS is sampled on the rising edge of TCK, and is used to place the Test Access Port controller into various states as defined in IEEE 1149.1. This lead is set high internally by an internal pull-up to VDD for normal framer operation. IEEE 1149.1 Test Port Serial Scan Data In: Serial test instructions and data are clocked into this lead on the rising edge of TCK. This input has an internal pull-up to VDD. IEEE 1149.1 Test Port Serial Scan Data Out: Serial test instructions and data are clocked out of this lead on the falling edge of TCK. When inactive, this 3-state output will be put into its high impedance state. IEEE 1149.1 Test Port Reset Lead: This lead will asynchronously reset the Test Access Port (TAP) controller. This lead is to be held low, asserted low or pulsed low (for a minimum duration of 20 ns) to reset the TAP controller on E1Mx16 power-up. This input has an internal pull-up to VDD.
TMS
AD3
I
TTLp
TDI
L2
I
TTLp
TDO
AE14
O(T)
TTL 4mA TTLp
TRS
AB3
I
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage DC input voltage Storage temperature range Ambient Operating Temperature Component Temperature x Time Moisture Exposure Level Relative Humidity, during assembly Relative Humidity ESD Classification LATCH-UP Symbol VDD VIN TS TA TI ME RH RH ESD LU 5 30 0 60 100 Min -0.5 -0.5 -55 -40 Max +6.0 VDD + 0.5 150 85 270 x 5
o
E1Mx16 TXC-04216
Unit V V
oC oC
Conditions Note 1 Note 1 Note 1 0 ft/min linear airflow Note 1 per EIA/JEDEC JESD22-A112-A Note 2 non-condensing Note 3 Meets JEDEC 78
Cxs
Level % % V
absolute value 1500
Notes: 1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability. 2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied. 3. Test method for ESD per MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS
Parameter Thermal resistance: junction to ambient Min Typ Max 15 Unit
oC/W
Test Conditions 0 ft/min linear airflow
POWER REQUIREMENTS
Parameter VDD IDD Power dissipation, PDD IDD Power dissipation, PDD Min 4.75 Typ 5.0 280 1400 310 1550 Max 5.25 310 1627 340 1785 Unit V mA mW mA mW STS-1 STS-1 STM-1 or STS-3 STM-1 or STS-3 Test Conditions
- 25 -
PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS
E1Mx16 TXC-04216
Input Parameters For CMOS Parameter VIH VIL Input capacitance (leads TESTp) Input capacitance (lead EXTCK) 7.5 30 Min 0.7 x VDD 0.3 x VDD Typ Max Unit V V pF pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25
Input Parameters For TTL Parameter VIH VIL Input capacitance (leads TCIpn, TPIpn, TNIpn/TLOSpn, QUIETpn and SELp) Input capacitance (all other leads) 7.5 Min 2.0 0.8 Typ Max Unit V V pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25
30
pF
Input Parameters For TTLp Parameter VIH VIL Input capacitance (leads TDI, TESTp, TXCTI3, TXCTI4 and TXCTI5) Input resistance (leads TDI, TESTp, TXCTI3, TXCTI4 and TXCTI5) Input capacitance (all other leads) Input resistance (all other leads) 7.5 Min 2.0 0.8 Typ Max Unit V V pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25
70
k
30 17.5
pF k
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
OUTPUT PARAMETERS
E1Mx16 TXC-04216
Output Parameters For CMOS 4mA Parameter VOH VOL IOL IOH Input capacitance (leads AAPAR, AA(7-0), BAPAR and BA(7-0)) Input capacitance (all other leads) 30 7.5 Min VDD - 0.7 0.4 4.0 -4.0 Typ Max Unit V V mA mA pF pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
Output Parameters For TTL 4mA Parameter VOH VOL IOL IOH Input capacitance 7.5 Min 2.4 0.4 4.0 -4.0 Typ Max Unit V V mA mA pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
Output Parameters For TTL 8mA Parameter VOH VOL IOL IOH Input capacitance 7.5 Min 2.4 0.4 8.0 -8.0 Typ Max Unit V V mA mA pF Test Conditions VDD = 4.75; IOH = -8.0 VDD = 4.75; IOL = 8.0
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
INPUT/OUTPUT PARAMETERS
E1Mx16 TXC-04216
Input/Output Parameters For TTL 4mA Parameter VIH VIL VOH VOL IOL IOH Input capacitance 30 2.4 0.4 4.0 -4.0 Min 2.0 0.8 Typ Max Unit V V V V mA mA pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
Input/Output Parameters For TTL 8mA Parameter VIH VIL VOH VOL IOL IOH Input capacitance 30 2.4 0.4 8.0 -8.0 Min 2.0 0.8 Typ Max Unit V V V V mA mA pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 4.75; IOH = -8.0 VDD = 4.75; IOL = 8.0
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET TIMING CHARACTERISTICS
E1Mx16 TXC-04216
Detailed timing diagrams for the E1Mx16 device are illustrated in Figures 4 through 14, with values of the timing intervals tabulated below the waveform diagrams. The tristate condition of a signal waveform is shown as midway between high and low. The timing parameters are measured at voltage levels of (VIH + VIL)/2 for input signals or (VOH + VOL)/2 for output signals, unless otherwise indicated. Where a waveform diagram describes both A and B bus signals, their symbols are combined in labeling the waveform (e.g., A/BADDp for AADDp and BADDp). Figure 4. Groups 1-4, Ports 1-4 E1 Transmit Timing
tCYC tPWL
TCIpn (Input)
tPWH
tSU tH
TPIpn/TNIpn (Input)
Note: p = 1 - 4 identifies a group of four ports n = 1 - 4 identifies one of four ports
Notes: 1. TCIpn is shown for TCLKIp = 0, where data is clocked in on falling edges. Data is clocked in on rising edges when TCLKIp =1. 2. For NRZ operation, TNIpn is not used for data input and may instead be used as the input for an external active low loss of signal indication TLOSpn. Otherwise, this lead must be held high.
Parameter TCIpn clock period TCIpn clock low time TCIpn clock high time TPIpn/TNIpn data setup time before TCIpn TPIpn/TNIpn data hold time after TCIpn
Symbol tCYC tPWL tPWH tSU tH
Min
Typ 488.28
Max
Unit ns ns ns ns ns
150 150 10 3.0
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 5. Groups 1-4, Ports 1-4 E1 Receive Timing tCYC tPWH
RCOpn (Output)
E1Mx16 TXC-04216
tPWL
tOD
RPOpn/RNOpn (Output)
Note: p = 1 - 4 identifies a group of four ports n = 1 - 4 identifies one of four ports
Note: RCOpn is shown for RCLKIp=0, where data is clocked out on rising edges. Data is clocked out on falling edges when RCLKIp=1.
Parameter RCOpn clock period RCOpn clock low time (RCLKIp = 0) RCOpn clock high time (RCLKIp = 0) RCOpn clock low time (RCLKIp = 1) RCOpn clock high time (RCLKIp = 1) RPOpn/RNOpn data delay after RCOpn
Symbol tCYC tPWL tPWH tPWL tPWH tOD
Min 480
Typ
Max 498
Unit ns ns
257 222 222 257 2.0 5.0 241 241
ns ns ns ns
Note: All output times are measured with a maximum 75 pF load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Figure 6. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus
tCYC A/BDCLK (Input) tSU(1) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) tSU(3) A/BDC1J1V1 (Input) A/BDINDp (Output) A/BA(7-0) A/BAPAR (Output) A/BADDp (Output) tOD(4) A/BAINDp (Output)
Add Bus TU/VT Time Slot when enabled
tPWH
tH(1) C1 tSU(2) Data tH(2) tH(3) C1 tD(1) tOD(2)
TU/VT Selected Occurs every four frames when provided in place of the H4 byte
A1
A2
Data
TU/VT Selected
J1
Data
Data
J1
V1
Drop Bus TU/VT Time Slot when enabled
tOD(3)
tOD(5) tOD(1)
Note: For illustration purposes, a single TU/VT (TU number 21) is shown. The V1 pulse may or may not be present. If it is not present, the H4 byte must be provided. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. DSPE edges are at payload boundaries.
Parameter DCLK clock period DLCK duty cycle tPWH/tCYC D(7-0)/DPAR data /parity setup time before DCLK D(7-0)/DPAR data /parity hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK DINDp drop bus indication output delay from DCLK A(7-0)/APAR data /parity out valid delay from DCLK A(7-0)/APAR data /parity to tristate delay from DCLK ADDp add indicator delay from DCLK AINDp add bus indication output delay from DCLK A(7-0)/APAR data /parity out tristate to driven delay from DCLK
Symbol tCYC
Load
Min
Typ 154.32
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 10 pF 45 pF 10 pF 45 pF 10 5.0 10 5.0 10 5.0 7.0 9.0 8.0 9.0 9.0 7.0
50
60
% ns ns ns ns ns ns
30 39 20 30 30 9.0
ns ns ns ns ns ns
Note: All output times are measured with the specified load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Figure 7. STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus
tCYC A/BDCLK (Input) tSU(1) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BDINDp (Output) A/BA(7-0) APAR (Output) A/BADDp (Output) A/BAINDp (Output)
tSU(3)
C1(1) C1(1)
tPWH
tH(1)
C1(2) C1(3) Data
TU/VT Selected J1 Byte STS-1 #1
STS-1 #2
STS-1 #3
Data STS-1 #1
tSU(2)
tH(2)
Occurs every four frames when provided in place of the H4 byte J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3 V1 STS-1 #1
tH(3)
tD(1) tOD(2)
Drop Bus TU/VT Time Slot selected when enabled
tOD(3)
TU/VT Selected
tOD(5) tOD(1) tOD(4)
Add Bus TU/VT Time Slot selected when enabled
Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus (number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. DSPE edges are at payload boundaries.
Parameter DCLK clock period DCLK duty cycle tPWH/tCYC D(7-0)/DPAR data /parity setup time before DCLK D(7-0)/DPAR data /parity hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK DINDp drop bus indication output delay from DCLK A(7-0)/APAR data /parity out valid delay from DCLK A(7-0)/APAR data /parity to tristate delay from DCLK ADDp add indicator delay from DCLK AINDp add bus indication output delay from DCLK A(7-0)/APAR data /parity out tristate to driven delay from DCLK
Symbol tCYC
Load
Min
Typ 51.44
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 10 pF 45 pF 10 pF 45 pF 10 5.0 10 5.0 10 5.0 7.0 9.0 8.0 9.0 9.0 7.0
50
60
% ns ns ns ns ns ns
30 39 20 30 30 9.0
ns ns ns ns ns ns
Note: All output times are measured with the specified load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 8. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus
E1Mx16 TXC-04216
tCYC A/BACLK (Input) tSU(2) A/BASPE (Input) tSU(1) A/BAC1J1V1 (Input) A/BA(7-0) A/BAPAR (Output) A/BADDp (Output) tOD(4) A/BAINDp (Output)
Add Bus TU/VT Time Slot when enabled
tPWH
tH(2)
Occurs every four frames when provided
tH(1) C1 tOD(2) tOD(5) tOD(1)
TU/VT Selected
J1
V1 tOD(3)
Note: For illustration purposes, a single TU/VT is shown. The location of this TU/VT corresponds to TU/VT number 21. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. ASPE edges are at payload boundaries.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity out valid delay from ACLK A(7-0)/APAR data /parity to tristate delay from ACLK ADDp add indicator delay from ACLK AINDp add bus indication output delay from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK
Symbo l tCYC
Load
Min
Typ 154.32
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 45 pF 10 5.0 10 5.0 7.0 7.0 7.0 7.0 5.0
50
60
% ns ns ns ns
31 16 24 24 7.0
ns ns ns ns ns
10 pF 45 pF
Note: All output times are measured with the specified load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 9. STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus
tCYC
A/BACLK (Input) A/BASPE (Input)
tSU(1) tH(1)
C1(1) J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3
E1Mx16 TXC-04216
tPWH tSU(2)
tH(2)
Occurs every four frames when enabled
A/BAC1J1V1 (Input) A/BA(7-0) A/BAPAR (Output) A/BADDp (Output)
V1 STS-1 #1
V1 STS-1 #2
V1 STS-1 #3
tOD(2)
TU/VT Selected
tOD(3)
tOD(5) tOD(1)
tOD(4)
A/BAINDp (Output)
Add Bus TU/VT Time Slot selected when enabled
Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus (number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABDp is written with a 1. The table omits A/B parameter prefixes. p=1-4 in both the table and figure. ASPE edges are at payload boundaries.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity out valid delay from ACLK A(7-0)/APAR data /parity to tristate delay from ACLK ADDp add indicator delay from ACLK AINDp add bus indication output delay from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK
Symbo l tCYC
Load
Min
Typ 51.44
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 45 pF 10 5.0 10 5.0 7.0 7.0 7.0 7.0 5.0
50
60
% ns ns ns ns
31 16 31 31 7.0
ns ns ns ns ns
10 pF 45 pF
Note: All output times are measured with the specified load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 10. Microprocessor Read Cycle Timing - Intel tH(1)
A(10-0) (Input)
E1Mx16 TXC-04216
Address
tD(5)
D(7-0) (Output)
Data tF(1) tSU(1) tD(1)
SELp (Input)
tSU(2)
RD (Input)
tH(2) tPW(1) tD(3)
tD(2)
RDYp (Output)
tD(4)
tF(2)
tPW(2)
Note: p=1-4 in both the table and figure.
Parameter Address setup time to SELp Address hold time after RD Data output float time after RD SELp setup time to RD RD pulse width SELp hold time after RD RDYp delay after SELp RDYp delay after RD RDYp float time after SELp Register read RDYp pulse width SPOT instruction read (Note 2) Data RAM read (Note 3)
Symbol tSU(1) tH(1) tF(1) tSU(2) tPW(1) tH(2) tD(2) tD(3) tF(2) tPW(2)
Min 0.0 3.0 2.0 10 40 0.0 2.0 4.0 2.0
Typ
Max
Unit ns ns
11
ns ns ns ns
10 20 10 0.0
ns ns ns ns ns ns
6 x SPcyc 9 x SPcyc
7 x SPcyc 33 x SPcyc
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Parameter Data output valid delay Register read only after RD Data output valid delay SPOT instruction read and data after RDYp RAM read only Data output tristate to driven delay after RD
Symbol tD(1) tD(4) tD(5)
Min 8.0
Typ
Max 28 0.0
Unit ns ns ns
2.0
Notes: 1. 2. 3. All output times are measured with a maximum 75 pF load capacitance. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) Excessive external microprocessor data RAM access could interfere with the E1Mx16 internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, E1Mx16 tries to slow down the external microprocessor access rate by lengthening the RDYp pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for each of the four E1Mx16 SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. For each group selected (via SELp) use 16 wait states for a read or write access if the RDYp signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the E1Mx16. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. For each group selected (via SELp) maintain no more than 16 microprocessor accesses per 125 s frame period. c. For each group selected (via SELp) maintain a minimum of 600 ns between microprocessor accesses.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 11. Microprocessor Write Cycle Timing - Intel
E1Mx16 TXC-04216
tH(1)
A(10-0) (Input)
Address tH(2)
D(7-0) (Input)
Data tSU(1) tSU(2) tSU(4)
SELp (Input)
tSU(3)
WR (Input)
tPW(1)
tD(1) tD(2)
RDYp (Output)
tF
tPW(2)
Note: p=1-4 in both the table and figure.
Parameter Address setup time to SELp Address hold time after WR Data input valid setup time to WR Data input hold time after WR SELp setup time to WR WR pulse width RDYp delay after SELp RDYp delay after WR RDYp float time after SELp
Symbol tSU(1) tH(1) tSU(2) tH(2) tSU(3) tPW(1) tD(1) tD(2) tF
Min 0.0 3.0 12 6.0 10 40 2.0 4.0 2.0
Typ
Max
Unit ns ns ns ns ns ns
10 20 10
ns ns ns
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Parameter Register write RDYp pulse width SPOT instruction write (Note 2) Data RAM write (Note 3) Data valid setup time to WR SPOT instruction write and data RAM write only
Symbol tPW(2)
Min
Typ
Max 0.0
Unit ns ns ns ns
5 x SPcyc 9 x SPcyc tSU(4) -1 x SPcyc
7 x SPcyc 29 x SPcyc
Notes: 1. 2. 3. All output times are measured with a maximum 75 pF load capacitance. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) Excessive external microprocessor data RAM access could interfere with the E1Mx16 internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, E1Mx16 tries to slow down the external microprocessor access rate by lengthening the RDYp pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for each of the four E1Mx16 SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. For each group selected (via SELp) use 16 wait states for a read or write access if the RDYp signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the E1Mx16. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. For each group selected (via SELp) maintain no more than 16 microprocessor accesses per 125 s frame period. c. For each group selected (via SELp) maintain a minimum of 600 ns between microprocessor accesses.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 12. Microprocessor Read Cycle Timing - Motorola tH(1) RD/WR (Input) A(10-0) (Input) Address tD(1) D(7-0) (Output) tSU(1) CS (Internal) SELp (Input) tPW(3) tD(2) DTACKp (Output) tD(3) tD(4) tD(5) Data tPW(1) tF(1)
E1Mx16 TXC-04216
tF(2)
Note: CS is an internal signal which is the logical OR of the SELp and LDS lead input signals. Its timing parameters refer to whichever of these signals controls the associated transition. p=1-4 in both the table and figure.
Parameter Address setup time and RD/WR setup time before CS Address hold time and RD/WR delay time after CS Data output float time after CS CS pulse width DTACKp driven delay after SELp DTACKp float time after SELp DTACKp stable delay after address becomes stable (Note 4) Register read DTACKp pulse width SPOT instruction read (Note 2) Data RAM read (Note 3)
Symbol tSU(1) tH(1) tF(1) tPW(1) tD(2) tF(2) tD(3) tPW(3)
Min 10 3.0 2.0 40 2.0 2.0 6.0
Typ
Max
Unit ns ns
11
ns ns
10 10 26 0.0
ns ns ns ns ns ns
6 x SPcyc 9 x SPcyc
7 x SPcyc 33 x SPcyc
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Parameter Data output delay after Register read only CS Data output delay after SPOT instruction read and data RAM read only DTACKp Data output tristate to drive delay after CS
Symbol tD(1) tD(4) tD(5)
Min 8.0
Typ
Max 28 0.0
Unit ns ns ns
2.0
Notes: 1. 2. 3. All output times are measured with a maximum 75 pF load capacitance. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) Excessive external microprocessor data RAM access could interfere with the E1Mx16 internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, E1Mx16 tries to slow down the external microprocessor access rate by lengthening the RDYp pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for each of the four E1Mx16 SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. For each group selected (via SELp) use 16 wait states for a read or write access if the DTACKp signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the E1Mx16. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. For each group selected (via SELp) maintain no more than 16 microprocessor accesses per 125 s frame period. c. For each group selected (via SELp) maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction read or data RAM read cycle, DTACKp stays high after tD(3). During a register read cycle, DTACKp settles to low after tD(3). DTACKp may go directly from a low to a high impedance state.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 13. Microprocessor Write Cycle Timing - Motorola
E1Mx16 TXC-04216
tH(1) RD/WR (Input) A(10-0) (Input) D(7-0) (Input) tSU(3) tSU(1) CS (Internal) SELp (Input) tPW(3) DTACKp (Output) tD(2) tD(3) tF tPW(1) Address tSU(2) Data tH(2)
Note: CS is an internal signal which is the logical OR of the SELp and LDS lead input signals. Its timing parameters refer to whichever of those signals controls the associated transition. p=1-4 in both the table and figure.
Parameter Address setup time and RD/WR setup time before CS Address hold time and RD/WR delay time after CS Data input setup time before CS Data input hold time after CS CS pulse width DTACKp driven delay after SELp DTACKp float time after SELp DTACKp stable delay after address becomes stable (Note 4) Register write DTACKp pulse width SPOT instruction write (Note 2) Data RAM write (Note 3)
Symbol tSU(1) tH(1) tSU(2) tH(2) tPW(1) tD(2) tF tD(3) tPW(3)
Min 10 3.0 12 6.0 40 2.0 2.0 6.0
Typ
Max
Unit ns ns ns ns ns
10 10 26 0.0
ns ns ns ns ns ns
5 x SPcyc 9 x SPcyc
7 x SPcyc 29 x SPcyc
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Parameter Data valid setup time to CS SPOT instruction write and data RAM write only
Symbol tSU(3)
Min -1 x SPcyc
Typ
Max
Unit ns
Notes: 1. 2. 3. All output times are measured with a maximum 75 pF load capacitance. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) Excessive external microprocessor data RAM access could interfere with the E1Mx16 internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, E1Mx16 tries to slow down the external microprocessor access rate by lengthening the RDYp pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for each of the four E1Mx16 SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. For each group selected (via SELp) use 16 wait states for a read or write access if the DTACKp signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the E1Mx16. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. For each group selected (via SELp) maintain no more than 16 microprocessor accesses per 125 s frame period. c. For each group selected (via SELp) maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction write or data RAM write cycle, DTACKp stays high after tD(3). During a register write cycle, DTACKp settles to low after tD(3). DTACKp may go directly from a low to a high impedance state.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Figure 14. Boundary Scan Timing
tPWL tPWH TCK (INPUT) tH(1) TMS (INPUT) tSU(1)
E1Mx16 TXC-04216
tH(2) TDI (INPUT) tSU(2)
tPW(1) TDO (OUTPUT) tD
tPW(1) TRS (INPUT)
Parameter TCK clock high time TCK clock low time TMS setup time before TCK TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay from TCK (Note 1) TRS Pulse Width
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tD tPW(1)
Min 50 50 3.0 2.0 3.0 2.0 20
Max
Unit ns ns
22 -
ns ns ns ns ns ns
Note 1:The output time (TDO) is measured with a maximum of 75 pF load capacitance.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET OPERATION
The following sections detail the internal operation of the E1Mx16.
E1Mx16 TXC-04216
BUS INTERFACE MODES The E1Mx16 supports the following bus modes of operation: - Drop Mode - Single Unidirectional Ring Mode - Multiplexer Mode - Dual Unidirectional Ring Mode Drop Mode In the drop mode of operation, a TU/VT is terminated from either the A or B Drop bus to the receive output of one of the four ports, without a return path in the transmit direction. Single Unidirectional Ring Mode In the single unidirectional ring mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path the A (or B) Add bus. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. Multiplexer Mode In the multiplexer mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path the B (or A) Add bus. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. Dual Unidirectional Ring Mode In the dual unidirectional ring mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path both the A and B Add buses. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
BUS MODE SELECTION
E1Mx16 TXC-04216
TU/VT bus mode selection is performed by the control bits defined in the table shown below. The n represents the port number (1-4) and p represents the group number (1-4). Note: Both the A and B Add buses power up in the high impedance state. A 0 must be written to control bits AAHZEp and BAHZEp for normal add bus operation. Mode Type Dropping only, from A Dropping only, from B Adding only, to A Adding only, to B Single unidirectional ring Single unidirectional ring Multiplexer, A in, B out Multiplexer, B in, A out Dual unidirectional ring Dual unidirectional ring TnSEL1p TnSEL0p 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 RnSELp DROP from Bus ADD to Bus 0 1 0 1 0 1 0 1 0 1 A B Add-only (2) Add-only (2) A B A B A B Drop-only (1) Drop-only (1) A B A B B A A and B B and A
Notes: 1. When the drop-only mode is selected, the ability to add a TU/VT is disabled, and the add bus is tristated. 2. The add-only feature is enabled by writing a 1 to control bit FRDISnp. The FEBE value and RDI states are transmitted as zero. However, the microprocessor can send an RDI, if required.
Bus Mode Selection for Port n in Group p
SDH/SONET ADD/DROP MULTIPLEXING FORMAT SELECTIONS The control bit settings for format selection are given in the table shown below, where p represents the group number (1-4). When the STS-1 format is selected, the buses are configured to operate at a bus rate of 6.48 Mbyte/s, instead of 19.44 Mbyte/s for VC-4/AU-3/STS-3 formats. Format STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format MOD1p 0 0 1 1 MOD0p 0 1 0 1
Format Selection for Group p
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DATA SHEET
DROP TU/VT SELECTION
E1Mx16 TXC-04216
The TU-12 (VT2) number selection register labels (RTUNnp), which consist of seven bits, are given in the following table. Selections are the same for each memory group which is selected via the SELp lead (p=1-4). An out of range value forces a high impedance state at the E1 receive interface. In addition, the FEBE and RDI states will be transmitted as zeros. Locations 04CH (port 1), 07CH (port 2), 0ACH (port 3), 0DCH (port 4) Bit 6 5 4 3 2 1 0 Meaning No TU/VT Selected STS-1 AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 No TU/VT Selected TU/VT Number 1 TU/VT Number 2 TU/VT Number 3
AU-3/TUG-3 or STS-1 ID 0 0 0 1 1 0 0 1 0 1
TU/VT Group Number 0 0 0
TU/VT Number 0 0
Drop TU/VT Selection for Port n in any Group p
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
ADD TU/VT SELECTION
E1Mx16 TXC-04216
The TU-12 (VT2) number selection register labels (TTUNnp), which consist of seven bits, are given in the following table. Selections are the same for each memory group which is selected via the SELp lead (p=1-4). An out of range value forces a high impedance state on the add bus. Locations 04DH (port 1), 07DH (port 2), 0ADH (port 3), 0DDH (port 4) Bit 6 5 4 3 2 1 0 Meaning No TU/VT Selected STS-1 AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 No TU/VT Selected TU/VT Number 1 TU/VT Number 2 TU/VT Number 3
AU-3/TUG-3 or STS-1 ID 0 0 0 1 1 0 0 1 0 1
TU/VT Group Number 0 0 0
TU/VT Number 0 0
Add TU/VT Selection for Port n in any Group p
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
BUS TIMING
E1Mx16 TXC-04216
Timing for adding a TU/VT to the add bus is derived from the like-named drop bus, or from the like-named add bus. Bus timing may be selected by using a lead, or through software. Upon power-up or a device reset, the SBTENp (Software Bus Timing Enable) control bit is reset to 0 and the ABUST lead controls bus timing selection. To enable the software to control timing, the SBTENp control bit must be first written with a 1, which will override the state placed on the ABUST lead. When SBTENp is 1, bus timing (add or drop bus timing) is controlled by the DRPBTp control bit. The various states associated with the bus timing selection are shown in the table below. ABUST lead Low High X X
Note: X = Don't Care
SBTENp 0 0 1 1
DRPBTp X X 0 1
Action Add bus timing selected by ABUST lead. Drop bus timing selected by ABUST lead. Add bus timing selected by DRPBTp bit. Drop bus timing selected by DRPBTp bit.
Bus Timing Selection for Group p
UNEQUIPPED OPERATION The E1Mx16 is capable of sending an unequipped channel or unequipped supervisory channel in all add modes of operation. Generally a channel which has either the UCHnEp bit or both the UCHnEp and USCHnEp bits set in the port provisioning registers will add an unequipped channel or unequipped supervisory channel for the TU/VT selected. An unequipped channel has a TU/VT pointer consisting of a valid NDF, size bits equal to 01, and a fixed pointer value of 105. The remaining VT overhead bytes and the payload are sent as zeros. The unequipped supervisory channel has an identical pointer to the unequipped channel, but sends a valid J2 byte, and valid BIP-2 bits and RDI-bit in V5, and valid RDI-bits in Z7. The E1Mx16 also sends a valid Z6 byte. The V5, RDI, Z7 RDI, and Z6 bytes can be set to zero by other control bits if they are not required. There are some differences in operation based on the UEAMEp bit in register 014H. The following table describes these differences. Unequipped Channel Generation for Group p UCHnEp/USCHnEp UEAMEp2 Add/Drop Mode Mux Drop From A B Single Unidirectional Ring Bidirectional Ring A B A B Drop Only A B A add High-Z Normal Normal High-Z Normal Normal High-Z High-Z B add Normal High-Z High-Z Normal Normal Normal High-Z High-Z
0
X1
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
UCHnEp/USCHnEp UEAMEp2
Add/Drop Mode Mux
Drop From A B
A add Unequipped2 Normal Unequipped High-Z Unequipped Unequipped High-Z High-Z High-Z Unequipped2 Unequipped High-Z Unequipped Unequipped High-Z High-Z
B add Normal Unequipped2 High-Z Unequipped Unequipped Unequipped High-Z High-Z Unequipped2 High-Z High-Z Unequipped Unequipped Unequipped High-Z High-Z
Single Unidirectional Ring 0 Bidirectional Ring
A B A B
Drop Only 1 Mux
A B A B
Single Unidirectional Ring 1 Bidirectional Ring
A B A B
Drop Only
A B
Notes: 1. 2. X = Don't Care (0 or 1). Only Multiplexed Mode is effected by the UEAMEp control bit. All other modes operate the same way regardless of the state of the UEAMEp control bit.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
DROP BUS MULTIFRAME ALIGNMENT
E1Mx16 TXC-04216
V1 byte alignment in the receive direction (from the drop bus) is established by using the H4 byte or the V1 reference pulse in the ADC1J1V1 and BDC1J1V1 signals. Depending on the format, one or three V1 pulses will be present in these signals. When the H4 byte is used to establish V1 byte alignment, the V1 pulse does not have to be present in the ADC1J1V1 or BDC1J1V1 signal. Writing a 1 to control bit DV1SELp selects the V1 pulse in the ADC1J1V1 and BDC1J1V1 signal to be used to establish the V1 byte location reference, while a 0 selects the H4 byte as the multiframe detector for establishing the V1 reference. The H4 multiframe detection circuits are disabled when the V1 pulse is used in place of the H4 byte. For STM-1 VC-4 operation, a single V1 pulse must occur three drop bus clock cycles every four frames following the J1 pulse. For STM-1 AU3/STS-3 operation, three V1 pulses must be present every four frames. Each V1 pulse must be present three clock cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte occurs six clock cycles after the V1 pulse. For STS-1 operation, one V1 pulse must be present. The V1 pulse must occur on the next clock cycle after J1, and when the SPE signal is high. The J1 pulse identifies the J1 byte location (defined as the starting location for the STS-1) in the POH bytes. The next column (first clock cycle) defines the VTs starting location. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the V1 bytes for the 21 VT2s are also aligned with respect to the V1 pulse. The timing relationships between J1, V1, and other signals are shown in the Timing Characteristics section. The H4 byte is used to identify the location of the V1 byte as shown in Figure 15 below: 2048 kbit/s TU/VT H4 (XXXX XX00) Of Previous SPE V1 35 Bytes H4 (XXXX XX01) V2 35 Bytes H4 (XXXX XX10) V3 35 Bytes H4 (XXXX XX11) V4 35 Bytes Figure 15. H4 Byte Floating VT Mode Bit Allocation The H4 byte is monitored for multiframe alignment when enabled. Loss of multiframe alignment is declared (AsDH4Ep, BsDH4Ep (s=1-3, p=1-4)) if two or more H4 byte values differ from those of a 2-bit counter for two consecutive multiframes. Recovery occurs when four consecutive sequential H4 byte values are detected once. - 50 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
ADD BUS MULTIFRAME ALIGNMENT
E1Mx16 TXC-04216
When drop bus timing is selected, add bus V1 alignment is based on the drop bus V1 pulse (A/BDC1J1V1) if DV1SELp is 1, or on the V1 reference signal that is generated by the H4 multiframe detectors in the drop bus side if DV1SELp is 0. When add bus timing is selected and a 0 is written to control bit DV1REFp, V1 byte alignment for the add bus is established by using the V1 pulses that must be present in the A/BAC1J1V1 signal. When add bus timing is selected and a 1 is written to control bit DV1REFp, V1 byte alignment for the add bus is determined by the drop bus V1 reference from either the A/BDC1J1V1 signal (if DV1SELp is 1), or from the internal V1 reference signal generated by the H4 multiframe detector in the drop bus direction (if DV1SELp is 0). The V1 pulse that is present in the A/BAC1J1V1 signal is ignored. Extreme care must be taken when using this V1 selection mode to prevent add bus V1 byte alignment slips. The control bit selection for both V1 add and drop bus byte alignment is described in the table below. Bus Timing Mode Drop bus timing selected DV1REFp 0 DV1SELp 0 Action Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location, and added TU/VT V1 byte starting location. V1 pulse in drop bus A/BDC1J1V1 signal ignored. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT V1 byte starting location, and added TU/VT V1 byte starting location. A/B drop bus H4 multiframe detector disabled. Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location. V1 pulse in drop bus A/BDC1J1V1 signal ignored. Add bus V1 alignment determined by the V1 pulse in the add bus A/BAC1J1V1 signal. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT starting location. Drop bus H4 multiframe detector disabled. Add bus V1 alignment determined by the V1 pulse in the add bus A/BAC1J1V1 signal. Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location. V1 pulses in drop bus A/BDC1J1V1 and add bus A/BAC1J1V1 signals are ignored. Add bus V1 alignment determined by the internal V1 pulse generated by the drop bus A/B H4 byte detector. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT V1 byte starting location, A/B drop bus H4 multiframe detector disabled. V1 pulse in add bus A/BAC1J1V1 signal is ignored. Add bus V1 alignment determined by the V1 pulse in the drop bus A/BDC1J1V1 signal.
Drop bus timing selected
0
1
Add bus timing selected
0
0
Add bus timing selected
0
1
Add bus timing selected
1
0
Add bus timing selected
1
1
Note:
X = Don't Care. Bus timing mode is selected via lead ABUST and control bits SBTENp, DRPBTp, as described earlier.
Add and Drop Bus V1 Reference Selection for Group p
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
PERFORMANCE COUNTERS
E1Mx16 TXC-04216
All performance counters are saturating, with the counters stopping at their maximum count. A counter is reset to zero by a hardware or software device reset, and when it is read by the microprocessor. The performance counters for port n of group p are also reset when a 1 is written to control bit RnSETCp. This bit is self-clearing, and does not require the microprocessor to write a 0 into its location. Counts that occur during the read cycle are held and updated afterwards. For a 16-bit counter, the low order byte must be read first, followed by reading the high order byte before the corresponding low order byte for another port is read. ALARM STRUCTURE All alarm indications are reported as unlatched and latched status bits. The latched bit of an alarm can be set on the positive transitions, negative transitions, both positive and negative transitions, or positive levels of the alarm. Reading a latched alarm bit clears the bit to 0. When control bit LATENp (address 011H, bit 4 of each memory group) is written with a 1, the latching of alarm transitions is enabled. Control bits IPOSp and INEGp (address 012H, bits 5 and 4 of each memory group) should be programmed to select the transition(s) on which latched bits are set. When LATENp is written with a 0, the latched bits are set on positive levels of the alarms. The IPOSp and INEGp bits are disabled when LATENp is set to 0. Alarm Hierarchy Mask Since multiple alarms at various levels can be detected simultaneously, a hierarchical masking scheme is employed in the E1Mx16. The E1Mx16 hierarchical mask effectively eliminates the confusion caused by the simultaneous reporting of multiple alarms and speeds up the identification of the alarm origins. The following table shows the hierarchical masking of unlatched low level alarms by high order alarms (depending on the Drop Bus selected and the Port selected). Masked cells indicate the lower level alarm masked by the high order alarms. For example: low level alarms J2LOL and J2TIM are masked when any of the following high order alarms/conditions are active: DLOC, OOR, UAISI, DH4E, AIS, LOP or SLER. Low Level Alarms masked by High Order Alarms High Order Alarms or Conditions DLOC OOR1 UAISI2, DH4E3 AIS, LOP Signal Label =001 or =000 SLER5 TCLM4 UAISI DH4E LOP AIS NDF SIZE * * * SLER RFI UNEQ J2LOL J2TIM RDIS RDIP RDIC * * * * TCUQ TCAIS TCLM * * * * TCLL TCTM TCODI TCRDI * * * *
*
* * * * *
* * * *
* * * *
* *
Notes: 1. OOR: Receive TU/VT Out Of Range is the condition when the receive TU/VT select bits (registers 0x4C, 7C, AC, DC) are set to an invalid value in which no TU/VT is selected (e.g. 0x00). There is no alarm bit to indicate this condition. 2. When control bit HEAISEp is 1 3. When control bit DV1SELp is 0 4. When control bit TCnENp is 1 5. When control bit 1BnRDIp = 0 When control bit 1BnRDIp = 1, then J2 Message Tracking is still enabled and SLER alarm will not mask J2LOL and J2TIM.
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DATA SHEET
INTERRUPT STRUCTURE
E1Mx16 TXC-04216
The interrupt indication register (address 020H of each memory group) contains the global software interrupt bit INTp and other interrupt indication bits. Each interrupt indication bit has an associated set of latched alarm bits. A mask bit is provided to enable the set of latched alarms to trigger their interrupt indication bit. For port alarms, the latched alarms of each port are further divided into several groups. A second level of mask bit is provided for each of these groups to mask out the interrupt indication bit of the port. For each interrupt indication bit, if its interrupt mask bits are 1, and one or more of its associated latched alarm bits are set, the interrupt indication bit will become 1; which in turn causes the software interrupt indication bit INTp to become 1. The E1Mx16 also generates a hardware interrupt at the tristate 8mA interrupt leads INTp/IRQp (p = 1 to 4), provided the hardware interrupt enable bit (HDWIEp) is 1. INT1/IRQ1 is an interrupt lead for the first group of four mappers (channels 1-4) and INT2/IRQ2, INT3/IRQ3 and INT4/IRQ4 are interrupt leads for the other three groups of four mappers. Addresses 016H and 021H (of each memory group) are the first set of interrupt mask registers. The additional mask registers for the port alarms are contained in addresses 017H, 018H and 019H (of each memory group). Upon power-up, when the RESETp bit (bit 7 in address 015H of each memory group) is written with a 1, or an active low is placed on the RESET lead, all the interrupt mask bits are cleared to 0. They must be initialized to 1 in order to enable the interrupt indication bits. Control bits IPOSp, INEGp and LATENp should also be programmed to determine how the latched alarms are to be set. Consider alarm AnAISp. Assume that HDWIEp is 1, the interrupt masks for AnAISp are 1, the control bits IPOSp and LATENp are 1, and control bit INEGp is 0. Since AnAISp is a port alarm, interrupt mask bit PnMSKp and the second level mask bit RPTnAp should be set to 1. A positive transition on AnAISp causes the latched bit of AnAISp to be set, which in turn sets the interrupt indication bit PORTnp. Then, both software and hardware interrupts occur. When an interrupt occurs, the external microprocessor can determine the alarm that caused the interrupt by reading the latched alarm registers that correspond to the interrupt indication bit and interrupt mask bit. The read cycles allow the microprocessor to determine what alarm has been set. When the register containing the latched alarm (e.g., AnAISp) has been read, the latched alarm bit is cleared, releasing the software interrupt (INTp and PORTnp returning to 0) and hardware interrupt. If there is more than one alarm in more than one alarm register, each of the corresponding latched alarm registers must be read before the interrupt is released. In addition, the hardware and software interrupt may be released by writing a 0 to the mask bits that correspond to the interrupt indication register. For AnAISp, the interrupt can be masked by writing 0 to PnMSKp or to the RPTnAp bits.
Note:Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Interrupt Registers for Group p
Address* 020H INTp EXTCKp Interrupt Indication Register (Address 020H) ASIDEp BSIDEp PORT4p PORT3p PORT2p
E1Mx16 TXC-04216
PORT1p
Interrupt Mask Register (Address 016H, 021H) 016H 021H 0 0 0 ECKMSKp 0 ASMSKp 0 BSMSKp 0 P4MSKp 0 P3MSKp 0 P2MSKp SPTMSKp P1MSKp
Additional Interrupt Mask Registers (Addresses 017H, 018H, 019H) 017H 018H 019H RPT4Ap TFIFO4Ap TPORT4p RPT4Bp TFIFO4Bp TPORT3p RPT3Ap TFIFO3Ap TPORT2p RPT3Bp TFIFO3Bp TPORT1p RPT2Ap TFIFO2Ap RFIFO4p RPT2Bp TFIFO2Bp RFIFO3p RPT1Ap TFIFO1Ap RFIFO2p RPT1Bp TFIFO1Bp RFIFO1p
Interrupt Indication ASIDE Registers (Addresses 022H, 024H) A Side Drop/Add Alarms (ASIDE) 022H 024H ADLOCp LEXTCp AALOCp 0 ADPARp 0 0 0 0 0 A3UAISIp A3DH4Ep A2UAISIp A2DH4Ep A1UAISIp A1DH4Ep
Interrupt Indication BSIDE Registers (Addresses 026H, 028H) B Side Drop/Add Alarms (BSIDE) 026H 028H BDLOCp SPTLOCp BALOCp WDTEXPp BDPARp 0 0 PERRp 0 0 B3UAISIp B3DH4Ep B2UAISIp B2DH4Ep B1UAISIp B1DH4Ep
Interrupt Indication PORTnp Registers (Addresses 030H, 04EH, 05AH, 03AH, 05EH, 05CH, 044H for Port 1) Port n Alarms (PORTnp) 030H 060H 090H 0C0H 04EH 07EH 0AEH 0DEH 05AH 08AH 0BAH 0EAH 03AH 06AH 09AH 0CAH 05EH 08EH 0BEH 0EEH 05CH 08CH 0BCH 0ECH 044H 074H 0A4H 0D4H AnAISp AnRDIPp AnTCUQp BnAISp BnRDIPp BnTCUQp RnFFEp AnLOPp AnRDICp AnTCAISp BnLOPp BnRDICp BnTCAISp 0 AnSIZEp 0 AnTCLMp BnSIZEp 0 BnTCLMp 1 AnNDFp 0 AnTCLLp BnNDFp 0 BnTCLLp TAnFEp AnRDISp AnJ2LOLp AnTCTMp BnRDISp BnJ2LOLp BnTCTMp TBnFEp AnRFIp AnJ2TIMp AnUNEQp 0 AnSLERp 0 0 BnSLERp 0 0 TnDAISp
AnTCODIp AnTCRDIp BnRFIp BnJ2TIMp BnUNEQp 0
BnTCODIp BnTCRDIp TnLOSp TnLOCp
*Note: Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Alarms, Interrupt Masks and Interrupt Indications A Side and B Side Alarms and Interrupts for Group p Latched Alarm Address2 022H Alarm Name ADLOCp AALOCp ADPARp 0 0 A3UAISIp A2UAISIp A1UAISIp 024H LEXTCp 0 0 0 0 A3DH4Ep A2DH4Ep A1DH4Ep 026H BDLOCp BALOCp BDPARp 0 0 B3UAISIp B2UAISIp B1UAISIp 028H SPTLOCp WDTEXPp 0 PERRp 0 B3DH4Ep B2DH4Ep B1DH4Ep BSMSKp SPTMSKp BSMSKp ASMSKp ECKMSKp Interrupt Mask or (016H or 021H) ASMSKp
E1Mx16 TXC-04216
Additional Interrupt Interrupt Indication Mask (if any) Bit (020H) ASIDEp
EXTCKp
ASIDEp
BSIDEp
(Note 1)
BSIDEp
Notes: 1. The SPOT alarm does not have an interrupt indication bit but it can still cause both software interrupt (INTp bit) and hardware interrupt (INTp/IRQp lead). 2. Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
PRELIMINARY TXC-04216-MB Ed. 2, October 2000
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DATA SHEET
A Side and B Side Port n Alarms and Interrupts for Group p
Additional Interrupt Interrupt Latched Indication Mask Alarm Bit (if any) Address2 (020H) (017H) RPTnAp PORTnp 03A port 1 06A port 2 09A port 3 0CA port 4
E1Mx16 TXC-04216
Latched Alarm Address2 030 port 1 060 port 2 090 port 3 0C0 port 4
Alarm Name
Interrupt Mask (021H) PnMSKp
Alarm Name
Interrupt Mask (021H) PnMSKp
Additional Interrupt Interrupt Indication Mask Bit (if any) (020H) (017H) RPTnBp PORTnp
AnAISp AnLOPp AnSIZEp AnNDFp AnRDISp AnRFIp AnUNEQp AnSLERp
BnAISp BnLOPp BnSIZEp BnNDFp BnRDISp
RFIEp (Note 1) RPTnAp
BnRFIp BnUNEQp BnSLERp 05E port 1 BnRDIPp 08E port 2 BnRDICp 0BE port 3 0 0EE port 4 0 BnJ2LOLp BnJ2TIMp 0 0 05C port 1 BnTCUQp 08C port 2 BnTCAISp 0BC port 3 0EC port 4 BnTCLMp BnTCLLp BnTCTMp BnTCODIp BnTCRDIp 0
RFIEp (Note 1) RPTnBp
04E port 1 AnRDIPp 07E port 2 AnRDICp 0AE port 3 0 0DE port 4 0 AnJ2LOLp AnJ2TIMp 0 0 05A port 1 AnTCUQp 08A port 2 AnTCAISp 0BA port 3 0EA port 4 AnTCLMp AnTCLLp AnTCTMp AnTCODIp AnTCRDIp 0 Notes:
1. RFIEp (address 012H, bit 3) is a common control bit for all four ports. A 1 enables the RFI indication to cause an interrupt. RPTnAp or RPTnBp is not required to be set to 1 to enable the interrupt for the RFI indication. A 0 disables an RFI indication from causing an interrupt. 2. Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Common Port n Alarms and Interrupts for Group p
Additional Interrupt Mask (if any) (018H* or 019H*) RFIFOnp Interrupt Indication Bit (020H*) PORTnp
E1Mx16 TXC-04216
Latched Alarm Address* 044 port 1 074 port 2 0A4 port 3 0D4 port 4
Alarm Name
Interrupt Mask (021H*) PnMSKp
RnFFEp 0 1 TAnFEp TBnFEp TnLOSp TnLOCp TnDAISp
TFIFOnAp TFIFOnBp TPORTnp
*Note: Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Interrupt and Alarm Control Bit Summary for Group p IPOSp 012H*: 5 0 X INEGp 012H*: 4 0 X HDWIEp 014H*: 0 0 X LATENp 011H*: 4 1 0 Interrupt Mask Bit X 0
E1Mx16 TXC-04216
Action on an Alarm No alarm event indication, or interrupt register indication. Alarm event register sets on positive levels of an alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive levels of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive levels of the alarm. Alarm event register sets on positive transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive transitions of the alarm. Alarm event register sets on negative transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on negative transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on negative transitions of the alarm. Alarm event register sets on positive and/or negative transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive and/or negative transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive and/or negative transitions of alarm.
X
X
0
0
1
X
X
1
0
1
1
0
X
1
0
1
0
0
1
1
1
0
1
1
1
0
1
X
1
0
0
1
0
1
1
0
1
1
1
1
1
1
X
1
0
1
1
0
1
1
1
1
1
1
1
*Note: Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
SDH/SONET AIS DETECTION
E1Mx16 TXC-04216
The E1Mx16 can detect an upstream AIS condition using the TOH H1/H2 (pointer) bytes or the TOH E1 (order wire) byte. When control bit SE1AISp (address 014H, bit 3 of each memory group) is 0, the H1/H2 bytes are monitored for an upstream AIS condition. When the MOD control bits (address 010H, bits 7 and 6 of each memory group) select the VC-4/TUG-3 format, the H11 and H21 bytes only are monitored for AIS. The monitoring of AIS in the two other H1n/H2n bytes is disabled. When the MOD control bits select the STS-3 or AU-3 format, each set of the three H1/H2 bytes per A Drop and B Drop buses is monitored for an AIS indication. Each of the three H1/H2 pointer bytes corresponds to the like-numbered AU-3/STS-1 signal (n=1-3). When the MOD control bits select the STS-1 format, the H1/H2 bytes per A Drop and B Drop buses are monitored for an AIS indication. If all ones are detected in the H1/H2 bytes (whose location is determined by the C1 pulse) for three consecutive frames, the alarm bits AsUAISIp in addresses 022H and 023H of each memory group (A bus detected H1/ H2 or E1 byte upstream AIS) or BsUAISIp in addresses 026H and 027H of each memory group (B bus detected H1/H2 or E1 byte upstream AIS) will set. Recovery occurs when a normal NDF (bits 1 through 4) in H1 is detected for three consecutive frames. A normal NDF is defined as a 0110, but 1110, 0010, 0100 and 0111 are also recognized as normal. The H1/H2 byte AIS detection circuits (when selected) for both the A and B Drop buses are disabled by writing a 0 to control bit HEAISEp (address 013H, bit 7 of each memory group). When control bit SE1AISp is 1, the E1n bytes for the port are monitored for an upstream AIS condition. When the MOD control bits select the VC-4/TUG-3 format, the E11 byte in both buses is monitored for AIS. The detection of the upstream AIS indication in the E12 and E13 bytes is disabled. When the MOD control bits select the AU-3/STS-3 format, each of the three E1n bytes in the A and B Drop buses are monitored for AIS. Each of the three E1n bytes corresponds to the like-numbered AU-3/STS-1 signal. For STS-1 operation, the single E1 byte is checked for the upstream AIS indication. Majority logic is used to determine if an E1n byte is carrying an upstream AIS indication. If 5 or more ones (at least 5 bits equal to 1 out of the 8 bits) are detected once in a A/B Drop bus E1n byte (whose locations are determined by the C1 pulse), the alarm bit AsUAISIp (A bus detected H1/H2 or E1 Byte AIS) or BsUAISIp (B bus detected H1/H2 or E1 Byte AIS) is set. Recovery occurs when 4 or more zeros (at least 4 bits equal to 0 out of the 8 bits) are detected once. The E1n byte AIS detection circuits (when selected) for both the A and B Drop buses are disabled by writing a 0 to control bit HEAISEp.
TU/VT POINTER TRACKING The starting location of the V1 byte is determined by either the V1 pulses in the A/BC1J1V1 signals or the H4 multiframe detection circuits. The TU/VT pointer bit assignment for the V1 and V2 bytes is shown below. The alignment is necessary to determine the starting locations of the V5 byte and the other bytes that are carrying the 2048 kbit/s format. V1 Byte 1 N 2 N 3 N 4 N 5 6 7 I 8 D 1 I 2 D 3 I SS-bits V2 Byte 4 D 5 I 6 D 7 I 8 D
I = Increment Bit D = Decrement Bit N = New Data Flag Bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) Negative Justification: Inverted 5 D-bits and accept majority rule Positive Justification: Inverted 5 I-bits and accept majority rule SS-bits (VT Size) = 10 for 2048 kbit/s - 59 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Pointer Bytes Bit Assignment
E1Mx16 TXC-04216
The pointer value is a binary number with a range of 0 to 139 for the 2048 kbit/s format. The pointer offset indicates the offset from the V2 byte to the first byte in the TU-12/VT2 mapping. The pointer bytes are not counted in the offset calculation. The pointer offset arrangement for this format is shown below. 2048 kbit/s TU-12/VT2 V1 105 106-138 139 V2 0 1-33 34 V3 35 36-68 69 V4 70 71-103 104 TU/VT Pointer Offset Locations
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Thirty-two independent pointer-tracking state machines are used in the E1Mx16, one for each of the A and B buses in each of the four groups of the four ports 1, 2, 3, and 4. The pointer tracking algorithm is illustrated in Figure 16. The pointer tracking state machine is based on the pointer tracking machine found in the latest ETSI requirements, and is also valid for both Bellcore and ANSI. When control bit PTALTEp at address 014H, bit 1 is 0, the transition from AIS to LOP is disabled (shown dotted), which is required in Bellcore recommendations.
3 x AIS_ind (Offset Undefined)
inc_ind (Incr. Offset) 3 x any_point 3 x new_point (Accept New Offset)
INC
NDF_enable (Accept New Offset) NDF_enable (Accept New Offset)
DEC
3 x AIS_ind (Offset Undefined)
3 x new_point (Accept New Offset) NDF_enable (Accept New Offset) 3 x new_point (Accept New Offset) 3 x any_point NDF_enable (Accept New Offset) 8 x inv_point (Offset Undefined) dec_ind (Decr. Offset) 3 x any_point
NDF
NORM
3 x new_point (Accept New Offset) 3 x AIS_ind (Offset Undefined) 3 x new_point (Accept New Offset)
3 x new_point (Accept New Offset)
3 x AIS_ind 8 x NDF_enable (Offset Undefined) (Offset Undefined)
LOP
8 x inv_point (Offset Undefined) NDF_enable (Accept New Offset) 3 x AIS_ind (Offset Undefined)
AIS
Figure 16. TU/VT Pointer Tracking State Machine
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
REMOTE DEFECT INDICATIONS
E1Mx16 TXC-04216
A 1-Bit/3-Bit RDI Selection bit - 1BnRDIp (bit 4 in registers 048H, 078H, 0A8H, 0D8H) - has been added to allow the user to select between the Enhanced 3-Bit RDI (1BnRDIp = 0) or Single Bit RDI (1BnRDIp = 1). The following sections describe the differences. V5 and K4 (Z7) Byte Coding (for 3-Bit RDI) Bits 5, 6 and 7 in the K4 (Z7) byte, in conjunction with bit 8 in the V5 byte, provide a detection scheme which is compliant with earlier versions of the RDI standard and also with enhanced TU/VT RDI capability. The enhanced version of RDI allows the user to differentiate between server, connectivity, and payload defects. Bit 8 in V5 is set equal to bit 5 in K4 (Z7). Bit 7 in K4 (Z7) is set to the inverse of bit 6 of K4 (Z7) to distinguish the enhanced version of RDI from the old version of RDI. It should be noted that when bits 6 and 7 in K4 (Z7) are either 01 or 10, the RDI indication is also influenced by Bit 8 of V5, as shown in the table below. When bits 6 and 7 are either 00 or 11, then RDI is determined solely by bit 8 in V5. This allows detection of an RDI originating from older equipment that generates the RDI in the V5 byte. The following table lists the RDI defect indications carried in the V5 and K4 (Z7) bytes. Bit 8 V5 Bit 5 K4 (Z7) Bit 6 K4 (Z7) Bit 7 K4 (Z7) 0 0 0 0 0 1 0 1 0 Definition No defect indications. No defect indications. Remote Payload Defect - Path Label Mismatch - Loss of Multiframe. No defect indications. Remote defect (old equipment). Remote Server Defect - VT Loss of Pointer - VT AIS detected - Upstream AIS detected (E1 or H1/H2 Bytes). Remote Connectivity Defect - Unequipped Signal Label - J2 Mismatch - J2 Loss of Lock Remote defect (old equipment).
0 1 1
1 0 0
1 0 1
1
1
0
1
1
1
RDI Bit Assignment for 3-Bit RDI
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Receive RDI Detection and Recovery (for 3-Bit RDI)
E1Mx16 TXC-04216
The RDI alarms are defined in the table below. The number of consecutive events for detection and recovery is controlled by control bit V5AL10p in address 014H, bit 2. The value of five is selected when the V5AL10p control bit is 0, and the value of ten is selected when the V5AL10p control bit is 1. AnRDICp BnRDICp 0 0 1 AnRDIPp BnRDIPp 0 1 0 AnRDISp BnRDISp 1 0 0
Action Remote Server Defect Indication, and old equipment RDI indication (Bit 8 in the V5 byte). Remote Payload Defect Indication. Remote Connectivity Indication.
RDI Alarm Definition for 3-Bit RDI Transmit RDI Generation (for 3-Bit RDI) An RDI is sent for the following unlatched alarm conditions in the V5 and K4 (Z7) overhead bytes of the VT added to the A or B Add bus, depending on the states of the RnSELp (active bus selected), TnSEL1p and TnSEL0p (bus enabled) control bits. The following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except DV1SELp). The variable s refers to the STS-1 or AU-3/TUG-3 identifier (s = 1 - 3). - When RDI enable (RDIENp) is 1, a Remote Server Defect Indication is sent for: - VT Loss of Pointer (A1LOPp, B1LOPp) - VT AIS (A1AISp, B1AISp) - A/B Drop Bus Upstream AIS in H1/H2 or the E1 byte (AsUAISIp, BsUAISIp), when HEAISEp is 1 - Microprocessor writes a 1 to T1RDISp - When RDI enable (RDIENp) is 1, a Remote Payload Defect Indication is sent for: - A/B Drop H4 Error (AsDH4Ep, BsDH4Ep), when DV1SELp is 0 - Mismatch signal label (A1SLERp, B1SLERp) - Microprocessor writes a 1 to T1RDIPp - When RDI enable (RDIENp) is 1, a Remote Connectivity Defect Indication is sent for: - Unequipped signal label (A1UNEQp, B1UNEQp), when UQAEp is 1 - J2 Mismatch (A1J2TIMp, B1J2TIMp), when J21AISEp is 1 - J2 Loss of Lock (A1J2LOLp, B1J2LOLp), when J21AISEp is a 1 - Microprocessor writes a 1 to T1RDICp - When RDI enable (RDIENp) is 0, the microprocessor can control RDI generation: - Microprocessor writes a 1 to T1RDISp to generate remote server defect indication. - Microprocessor writes a 1 to T1RDIPp to generate remote payload defect indication. - Microprocessor writes a 1 to T1RDICp to generate remote connectivity defect indication.
Note: The microprocessor may send an RDI by writing to the above control bits at any time, including the add-only mode. To prevent contention between the internal logic and full microprocessor control, the RDIENp control bit should be written with a 0 when microprocessor control is intended. The priority used for sending RDI if more than one of the microprocessor controls are set is: Server, Connectivity, and Payload. When RDIEN = 1 and no defects are generated then K4 bits 5,6,7 = 001.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
V5 and K4 (Z7) Byte Coding (for 1-Bit RDI)
E1Mx16 TXC-04216
In the Receive (Rx) direction bit 8 in the V5 byte is used to detect Remote Defect Indications. Bits 5, 6, and 7 in the Rx K4(Z7) byte are not looked at for detecting RDI and can have any incoming value, 0 or 1. For transmitting 1-Bit RDI, bit 8 in V5 byte will be set as shown below and bits 5,6,7 in the K4(Z7) byte will be sent as 0. See table below:
Bit 8 V5 0 1
Bit 5 K4 (Z7) Bit 6 K4 (Z7) Bit 7 K4 (Z7) 0 0 0 0 0 0
Definition No defect indications. Remote Defect Indication.
RDI Bit Assignment for 1-Bit RDI Receive RDI Detection and Recovery (for 1-Bit RDI) The RDI alarm is defined in the table below. The number of consecutive events for detection and recovery is controlled by a Common Register - Provisioning Control bit V5AL10p (register 014H, bit 2). When V5AL10p = 0, the value is 5; when V5AL10p = 1, the value is 10. A Remote Defect Indication is indicated by alarm indication bit AnRDISp/BnRDISp. Alarm indication bits AnRDIPp/BnRDIPp and AnRDICp/BnRDICp are disabled and will always be equal to zero when 1-Bit RDI mode is selected. AnRDICp BnRDICp 0 0 AnRDIPp BnRDIPp 0 0 AnRDISp BnRDISp 0 1
Action No defect indications. Remote Defect Indication.
RDI Alarm Definition for 1-Bit RDI
Transmit RDI Generation (for 1-Bit RDI) An RDI is sent for the following unlatched alarm conditions in the V5 overhead byte of the VT added to the A or B Add bus, depending on the states of the RnSELp (active bus selected), TnSEL1p and TnSEL0p (bus enabled) control bits. The following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except DV1SELp). The variable s refers to the STS-1 or AU-3/TUG-3 identifier (s = 1 - 3). - When RDI enable (RDIENp) is 1, a remote defect indication (bit 8 in V5=1; bits 5,6,7 in K4(Z7)=0) is sent for: - VT Loss of Pointer (AnLOPp, BnLOPp) - VT AIS (AnAISp, BnAISp) - A/B Drop Bus Upstream AIS in H1/H2 or the E1 byte (AsUAISIp, BsUAISIp), when HEAISEp is 1. - Unequipped Signal Label (AnUNEQp, BnUNEQp), when UQAEp is 1. - J2 Loss of Lock (A1J2LOLp, B1J2LOLp), when J21AISEp is a 1. - J2 Mismatch (A1J2TIMp, B1J2TIMp), when J21AISEp is 1 - Microprocessor writes a 1 to T1RDISp to generate a Remote Defect Indication.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
- When RDI enable (RDIENp) is 0, the microprocessor can control RDI generation: - Microprocessor writes a 1 to T1RDISp to generate Remote Defect Indication.
E1Mx16 TXC-04216
Note: For 1-Bit RDI mode the following unlatched alarm conditions will not generate a Remote Defect Indication: - A drop H4 error (AsDH4Ep, BsDH4Ep), when DV1SEL is a 0. - Mismatch signal label (AnSLERp, BnSLERp). Note: For 1-Bit RDI mode the following microprocessor control bits are disabled and will not generate a Remote Defect Indication: - Microprocessor writes a 1 to TnRDIPp. - Microprocessor writes a 1 to TnRDICp.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
OVERHEAD COMMUNICATIONS BIT ACCESS
E1Mx16 TXC-04216
Microprocessor access is provided for the eight overhead communications bits (O-bits) carried in the two justification control (JC) bytes in the multiframe format, e.g., in a 2048 kbit/s TU/VT, shown partially below. The bits in the justification control byte are numbered 1 through 8, starting with C1 as bit 1. Other Bytes J2 Byte JC Byte 1 C1 C2 O O O O R R
32 Bytes - Information R R R R R R R R
N2 (Z6) Byte JC Byte 2 C1 C2 O O Other Bytes O-bit Placement in a 2048 kbit/s TU/VT O O R R
In the receive direction, the eight O-bits are stored in eight 8-bit registers (A and B for each group of 4 ports) and these registers are updated each frame. The two O-bit nibbles that form a byte in the registers for receiving and transmitting are from the same multiframe. Bits 3 through 0 in an O-bit register correspond to bits 3 through 6 (C1C2 OOOO RR) in the first justification control byte, and bits 7 through 4 in an O-bit register correspond to bits 3 through 6 in the second justification control byte, as shown below. Second Justification Control Byte Bit Register 3 7 4 6 5 5 6 4 First Justification Control Byte 3 3 4 2 5 1 6 0
O-bit Assignment Memory Map
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
J2 BYTE PROCESSING
E1Mx16 TXC-04216
There are two possible received J2 message sizes, 16 bytes (ITU-T), or 64 bytes (ANSI). The E1Mx16 is capable of dimensioning the transmit (and receive) RAM memory segment to the two sizes (16-byte or 64-byte). In addition, two modes of operation are provided for the 16-byte (ITU-T) format: a microprocessor read mode, and a compare read mode. The following table lists the various control states associated with J2 processing. J2nSIZEp 0 J2nCOMp 0 Action Transmit and receive J2 segments are configured for the 16-byte J2 message size. Microprocessor read for the dropped J2 message. J2 alarms are disabled. Transmit and receive J2 segments are configured for the 16-byte J2 message size. For receiving, a 16-byte microprocessor message is written into a 16-byte segment for comparison against the received message. The written message must start with the multiframe indicator written into the starting location of the segment. Transmit and receive J2 segments are configured for the 64-byte J2 message size. Microprocessor read for the dropped J2 message. J2 alarms are disabled. The tandem connection feature must be disabled by setting TCnENp=0 for the port.
0
1
1
X
Note: X = Don't Care
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
The ITU-T defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most significant bit (bit 1) of the message. The remaining 7 bits in each byte carry a data message, as illustrated below. Bit 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 6 7 8
16-Byte J2 Message
ITU-T 16-Byte J2 Message Format The definitions (ITU-T) shown below will be used in the following discussion of the J2 16-byte message comparison function. The memory locations apply to each memory group.
ITU-T Definitions
RxTI - Received TTI (Trail Trace Identifier) ExTI - Expected TTI (Trail Trace Identifier) AcTI - Accepted TTI (Trail Trace Identifier)
E1Mx16 Definitions
Incoming J2 trace message (Real Time) Microprocessor-written trace (reference) message. A Side (X50H - X5FH) B Side (XD0H - XDFH) Received stable trace message. A Side (X40H - X4FH) B Side (XC0H - XCFH)
The J2 16-byte message comparison works according to the following steps: 1. The microprocessor-written reference message (ExTI) locations should be initialized with the correct J2 16-byte message before enabling the J2 message comparison function. 2. The J2 message comparison function is then enabled (J2nCOMp = 1; J2nSIZEp = 0) and immediately the J2 Loss of Lock alarm will be active (J2nLOLp = 1) and the J2 Trace Identifier Mismatch alarm will be inactive (J2nTIMp = 0). This is the first step in the sequence - to initialize these alarms. 3. The incoming trace message (RxTI) is received, and the J2 comparison circuit searches for the J2 alignment pattern (Bit 1: 1000...0 pattern). 4. J2 alignment pattern is found and the Received stable trace message (AcTI) locations are updated with this incoming trace message (RxTI).
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
5. The incoming trace message (RxTI) is then checked for three consecutive 16-byte message repeats. 6. If an error occurs before step 5 is completed, the sequence repeats, starting at step 3 (searching for the alignment pattern). 7. If the incoming trace message (RxTI) repeats three times in a row (after the alignment pattern is detected) without an error then this is an in-lock condition, and the J2 Loss of Lock alarm is reset (J2nLOLp = 0). Note that at this time the J2 mismatch alarm is still inactive (J2nTIMp =0). 8. Once the incoming trace message is in-lock, the stable message (AcTI), is compared against the microprocessor-written reference message (ExTI), byte for byte, for 16 bytes (the length of the multiframe message). If they compare (AcTI = ExTI), a match is declared, with no mismatch alarm (J2nTIMp = 0). If they do not compare (AcTI ExTI), a mismatch alarm is declared (J2nTIMp = 1). A J2 mismatch alarm results in RDI and receive line AIS being sent continuously, when enabled. There is no Loss of Lock alarm (J2nLOLp = 0) because the incoming trace message (RxTI) is stable. 10. If the incoming message (RxTI) changes for three consecutive 16-byte messages, a loss of lock alarm (J2nLOLp = 1) occurs and the sequence starts again from the beginning (step 2). Summary of J2 Alarms: - J2 Loss of Lock (J2nLOLp) is a comparison between the Received stable message (AcTI) and the Receive incoming (real time) message (RxTI). - Declare Lock (J2nLOLp = 0) when AcTI = RxTI for 3 consecutive set of 16 bytes. - Loss of Lock (J2nLOLp = 1) when AcTI RxTI on at least 1 byte in each of 3 consecutive 16-byte messages - J2 Trace Identifier Mismatch (J2nTIMp) is a comparison between the Received stable message (AcTI) and the microprocessor-written reference message (ExTI). - Declare Mismatch (J2nTIMp = 1) when AcTI ExTI on any byte once lock is declared. - Clear Mismatch (J2nTIMp = 0) when AcTI = ExTI. See Note below. Note: A mismatch alarm is declared for the following reasons. 1) A valid mismatch alarm would be declared when the stable message (AcTI) does not match the reference message (ExTI). 2) An invalid mismatch alarm would be declared if the correct start-up procedure was not used and the reference message (ExTI) was not loaded before enabling the J2 comparison function. 3) Another reason for getting an invalid mismatch alarm would be if the reference message was written with the wrong message value. In any case if the incoming message is stable (or In-Lock - J2nLOLp = 0) then the only way to clear the mismatch alarm would be to cause a Loss of Lock condition.
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Suggested J2 16-byte Message Comparison Start-up Procedure: From Start-up: 1) At transmitting device - Send a "valid" message (TxTI).
E1Mx16 TXC-04216
2) At receive device -a) Load microprocessor-written reference message (ExTI) with a "valid" message. b) Enable J2 Message Comparison. Note: 1 and 2 are interchangeable If Changing Messages: 1) At receive device - Load microprocessor-written reference message (ExTI) with a "new valid" message. 2) At transmitting device - Send a "new valid" message (TxTI). Note: If 1 is not done before 2 then a mismatch alarm is declared. If this occurs it is not a valid mismatch (assuming that the messages are correct). Following the start-up procedure above will assure that the Trace Identifier Mismatch alarm only activates when the messages do not match. There is the possibility that a mismatch alarm will activate by not following the correct start-up procedure, upon which the following should be done: 1) At Receive device - verify that microprocessor-written (reference) message (ExTI) is correct 2) At Receive device - verify that the stable message (AcTI) is correct by examining J2nLOLp. Since AcTI is written only once at the beginning of the algorithm, when searching for the J2 alignment pattern, if no Loss of Lock alarm is set then the incoming message RxTI is still the same valid message in AcTI. Now force a Loss of Lock condition by using the microprocessor to overwrite any byte of the stable message (AcTI) with a value that corrupts the alignment pattern (i.e., address X40=0x00). The Loss of Lock alarm will set, and then the re-start the algorithm from the beginning, which resets the mismatch alarm, and starts searching again for the alignment pattern.
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N2 (Z6) BYTE PROCESSING (Tandem Connection)
E1Mx16 TXC-04216
The Tandem Connection feature is enabled for a TU/VT by writing a 1 to control bit TCnENp, when control bit J2nSIZEp is a 0. When control bit TCnENp is written with a 0, the tandem connection feature is disabled. See address 051H, bit 4 of each memory group, in the Memory Map Descriptions section for more detail on TCnENp. The bit placement in a received N2 (Z6) byte is as shown below: Bit 1 BIP-2 2 3 1 4 AIS Indication 5 TC REI 6 TC OEI (FEBE) 7 8
Trace ID TC RDI/ODI
BIP-2, AIS Indication, TC REI and TC OEI Processing One or two errors may be detected in the TC BIP-2 comparison, and they are counted individually in an 8-bit counter when control bit BLOCKp is written with a 0 (An TC BIP-2 Error Counter, Bn TC BIP-2 Error Counter). When control bit BLOCKp is written with a 1, one or two parity errors are counted as a single block error. A tandem connection AIS alarm (AnTCAISp, BnTCAISp) is declared when bit 4 is equal to 1 for five consecutive frames. Recovery occurs when bit 4 is equal to 0 for five consecutive frames. An 8-bit counter (An TC REI Counter, Bn TC REI Counter) is provided for counting the number of REI bits received as equal to 1 in bit 5 (TC REI) in the N2 (Z6) byte. A REI indication (a 1) indicates that the distant end has detected one or two errors when the BIP-2 calculated for frame f-1 (all the bytes) is compared against the BIP-2 value carried in the N2 (Z6) byte in frame f. An 8-bit counter (An TC OEI Counter, Bn TC OEI Counter) is provided for counting the number of OEI bits received as equal to 1 in bit 6 (TC OEI) in the N2 (Z6) byte. An OEI indication (a 1) indicates that the distant end has detected one or two errors when the BIP-2 calculated for frame f-1 is compared against the BIP-2 value carried in the V5 byte in frame f. Bits 7 and 8 A multiframe alignment pattern, a trace identifier message, and TC RDI and TC ODI indications are assigned to bits 7 and 8 in the frames of a 76-frame structure, as shown below: Frame No. 1-8 9 - 12 13 - 16 17 - 20 65 - 68 69 - 72 73 74 75 76 N2 (Z6) Byte, Bits 7 and 8 Definition Frame Alignment, 1111 1111 1111 1110 TC Trace ID Byte No. 0 (1 C1 C2 C3 C4 C5 C6 C7) TC Trace ID Byte No. 1 (0 X X X X X X X) TC Trace ID Byte No. 2 (0 X X X X X X X) TC Trace ID Byte No. 14 (0 X X X X X X X) TC Trace ID Byte No. 15 (0 X X X X X X X) Bit 7 = 0, Bit 8 = TC RDI Bit 7 = TC ODI, Bit 8 = 0 Bit 7 = 0, Bit 8 = 0 Bit 7 = 0, Bit 8 = 0
21 - 24 thru 61 - 64 TC Trace ID Bytes No. 3 thru 13
Loss of multiframe (status bits AnTCLMp, BnTCLMp) occurs when four consecutive Frame Alignment Signals (1111 1111 1111 1110) are detected in error (i.e., one or more errors in each FAS). Multiframe alignment is
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recovered when three consecutive non-errored FAS are found.
E1Mx16 TXC-04216
The TC trace identifier message comparison is based on the same state machine as that used for the 16-byte J2 message. If the message is not locked, an AnTCLLp or BnTCLLp alarm is declared. After TC lock is established, a comparison is performed between the microprocessor-written TC and the contents of the incoming message. The message consists of TC Trace ID bytes 0 to 15. A TC Trace Identifier Mismatch (AnTCTMp, BnTCTMp) alarm is declared when any byte does not match. Recovery occurs when there is a match between the microprocessor message and the accepted message. Bit 8 in frame 73 is defined as a Tandem Connection Remote Defect Indication (TC RDI). A TC RDI alarm occurs when a 1 has been detected in bit 8 in frame 73 for 5 consecutive multiframes (where each multiframe is 38 ms). The TC RDI alarm state is exited when bit 8 is equal to 0 for 5 consecutive multiframes. An alarm indication is reported as AnTCRDIp or BnTCRDIp. Bit 7 in frame 74 is defined as a Tandem Connection Outgoing Defect Indication (TC ODI). A TC ODI alarm occurs when a 1 has been detected in bit 7 in frame 74 for 5 consecutive multiframes (where each multiframe is 38 ms). The TC ODI alarm state is exited when bit 7 is equal to 0 for 5 consecutive multiframes. An alarm indication is reported as AnTCODIp or BnTCODIp. Tandem Connection Unequipped Status Unequipped Tandem Connection detection is provided. Five or more consecutive received tandem connection N2 (Z6) bytes equal to XX00 0000 result in a TC unequipped indication (AnTCUQp, BnTCUQp). The alarm state is exited when five or more consecutive received tandem connection N2 (Z6) bytes are not equal to XX00 0000 (X is a don't care). Note that bits 1 and 2 of the N2 (Z6) byte are not taken into consideration and do not affect the unequipped indication. TUG-3 NULL POINTER INDICATOR For STM-1 TUG-3 format, the E1Mx16 has the option to generate and transmit a Null Pointer Indicator (NPI) for one or more of the TUG-3s, as shown below.
TUG-3A 1 N P I 86 1 N P I TUG-3B 86 1 N P I TUG-3C 86
VC-4 P O H
1
261
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NPI Structure
E1Mx16 TXC-04216
Three control bits (NPIAp, NPIBp and NPICp in address 010H, bits 2-0 of each memory group) are provided for selecting one or more of the TUG-3 NPIs. The three control bits are enabled when the MOD1p and MOD0p control bits are 11 (TUG-3/VC-4 format). The NPI consists of three bytes, starting with row 1. The table below shows the bit assignment for the first two bytes. Bit Row 1 Row 2 1 1 1 2 0 1 3 0 1 4 1 0 5 0 0 6 0 0 7 1 0 8 1 0
NPI Bit Assignment The third NPI byte is designated as fixed stuff and is transmitted as zero. The remaining cross-hatched bytes in the first two columns of the TUG-3 are tristated on the add bus. When a 1 is written to control bit NULLZp in address 013H, bit 3 of each memory group and the NPI feature is enabled (i.e., NPIAp, NPIBp or NPICp is a 1) the bytes following the NPI bytes are transmitted as zeros. When the NULLZp bit is a 0, the bytes following the NPI bytes are tristated.
E1 LOOPBACK CAPABILITY The E1Mx16 provides two types of E1 loopbacks, called facility and line loopbacks (i.e., at the facility side and at the line side, as illustrated in Figure 17). In Figure 17, the E1 Transmit Data and Clock goes into the E1Mx16, while the E1 Receive Data and Clock comes out of the E1Mx16. Facility loopback for port n of group p, enabled when a 1 is written to control bit FnLBKp, directs the incoming E1 Transmit Data and Clock to the outgoing Receive Data and Clock signal. Line loopback for port n, enabled when a 1 is written to control bit LnLBKp, routes the outgoing E1 Receive Data and Clock signal (instead of the incoming E1 Transmit Data and Clock) to the SDH/SONET transmitter.
FnLBKp BYPASnp From Desynchronizer 0 1 ANAnENp ANAnTxp Facility Loopback Line Loopback E1 LINE PRBS Analyzer REC NRC ANAnOOLp 1 HDB3 Coder 0
NRZ Rail
1 0
Receive Data & Clock (NRZ, Rail)
XMIT NRZ 0 To Synchronizer 1 PRBS Generator
0 1
NRZ NRZ
HDB3 Coder
1 0 Transmit Data & Clock (NRZ, Rail)
LnLBKp BYPASnp
PRBSnENp
Clock
Figure 17. Facility and Line Loopbacks - 73 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
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PRBS PATTERN GENERATOR AND ANALYZER
E1Mx16 TXC-04216
Each port has a data generator and analyzer for 215-1 PRBS patterns, as illustrated in Figure 17. The PRBS generator is enabled when a 1 is written to control bit PRBSnENp. The PRBS pattern will be synchronous to the clock driving the HDB3 decoder. When a 1 is written to ANAnENp control bit, the PRBS analyzer is enabled. When control bit ANAnTxp is 0, the analyzer will sample the receive NRZ clock and data (REC NRZ) signals. When the control bit ANAnTxp is 1, the internal transmit NRZ clock and data signals (XMIT NRZ) will be sampled by the analyzer.
RESETS The E1Mx16 has several reset options. These include a full hardware and software device reset, partial software resets, and counter software resets. All of the software reset bits are self-clearing (i.e., they do not require 0 to be written to a register location after the reset is applied by setting the bit to 1). Note that the self-clearing function requires the presence of the clock signal provided to the EXTCK lead. Upon power-up, when the RESETp bit (address 015H, bit 7 of each memory group) is written with a 1, or an active low signal is placed on the common RESET lead, the add bus data and the port E1 interfaces are forced to a high impedance state until the device is initialized. The control bits AAHZEp and BAHZEp (address 010H, bits 5 and 4 of each memory group) must be written with zeros to enable the add bus interfaces. The RnENp control bits must be programmed to 1 to activate the line interfaces. In addition, the AAINDp, BAINDp, AADDp and BADDp leads are forced off. All performance counters are reset, and the alarms (except AnLOPp and BnLOPp) are reset. The control bits (except those shaded in the Memory Map) are also forced to zero, and the various FIFOs are re-initialized. The shaded bits are contained in the Data RAM, and these can be initialized by writing a 1 to INITSPp (see Memory Map Descriptions, address 015H, bit 0). A hardware reset can only be applied after the clocks are stable, and must be present for a minimum duration of 150 ns. Writing a 1 to the RnSETSp software reset control bit for any of the ports resets the port n performance counters, re-initializes the FIFO, and clears the alarms, except the AnLOPp and BnLOPp alarms, which will set for port n. The loss of pointer alarms will recover when a valid pointer is received. The control bits will not be reset. Writing a 1 to the RnSETCp counter reset control bit for any of the ports resets the performance counters for that port. This feature allows the performance measurements to start at the same time for a port. Writing a 1 to control bit RESTABp (address 015H, bit 6) resets the alarms for the A bus and for LEXTCp (i.e., addresses 022H to 025H of each memory group). Writing a 1 to control bit RESTBBp (address 015H, bit 5 of each memory group) resets the alarms for the B bus and the SPOT alarms (i.e., addresses 026H to 028H of each memory group). Note that a hardware reset will automatically trigger all the software reset bits. Software reset bit RESETp will trigger all RnSETSp, all RnSETCp, RESTABp and RESTBBp automatically. A RnSETSp will also automatically trigger a RnSETCp.
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START-UP PROCEDURE
E1Mx16 TXC-04216
The following procedure should be followed to start up the E1Mx16 in a known good state from initial power-on, or from a hardware or software reset. Initial power-on: ---------------- (start from step 1) From a hardware reset: ------ (start from step 2) From a software reset: ------- (start from step 4) (1) (2) (3) (4) (5) (6) (7) Power up Device Apply Hardware Reset (lead B4) Load SPOT microcode (see flowchart in Figure 23) Apply Software Reset (RESETp=1; register 0x015 = 0x80 of each memory group) Initialize Data RAM (INITSPp=1; register 0x015 = 0x01 of each memory group) Load all Control Registers for user specific operation Clear any alarms that may have been latched, by generating the following resets: - RESTABp and RESTBBp (register 0x015 = 0x60 of each memory group) - R1SETSp (register 0x052 = 0x80 of each memory group) - R2SETSp (register 0x082 = 0x80 of each memory group) - R3SETSp (register 0x0B2 = 0x80 of each memory group) - R4SETSp (register 0x0E2 = 0x80 of each memory group) (8) Clear AnLOPp and BnLOPp by reading the corresponding Port Status Registers: - Clear A1LOPp (read register 0x030 of each memory group) - Clear A2LOPp (read register 0x060 of each memory group) - Clear A3LOPp (read register 0x090 of each memory group) - Clear A4LOPp (read register 0x0C0 of each memory group) - Clear B1LOPp (read register 0x03A of each memory group) - Clear B2LOPp (read register 0x06A of each memory group) - Clear B3LOPp (read register 0x09A of each memory group) - Clear B4LOPp (read register 0x0CA of each memory group)
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POINTER LEAK RATE CALCULATIONS
10 SEC
E1Mx16 TXC-04216
Set FIFO Leak Rate to 04 Hex (Note 3)
Measure 1 Second, add to C (Note 4)
10 SEC
Calculate FIFO Leak Rate (Note 5)
Start AIS, LOP LOS, NDF or RESET
Set FIFO Leak Rate (Note 6)
Subt Oldest Add Newest (Note 7)
Measure 1 Second (Note 6)
Notes: 1. The procedure described in Notes 2 through 8 below must be performed independently for each of the four ports in each memory group of the E1Mx16 device. 2. The procedure shown in the diagram above uses a ten-second sliding window with a resolution of one second. 3. The initial FIFO Leak Rate Register value (in memory map address 049H, 079H, 0A9H or 0D9H of each memory group) must first be set to 04 Hex. 4. Measure ten consecutive one-second samples from the Positive and Negative Stuff Counters being used. Store all ten difference values, i.e., S1 = POS STUFF COUNT1 - NEG STUFF COUNT1, S2 = POS STUFF COUNT2 - NEG STUFF COUNT2, and so on through S10 = POS STUFF COUNT10 - NEG STUFF COUNT10. There are eight pairs of stuff counters in the E1Mx16; care should be taken to use the pair appropriate to the programmed configuration of the device. The counters are located at addresses 032H, 062H, 092H, 0C2H (A side) and 03CH, 06CH, 09CH, 0CCH (B side). 5. Calculate the leak rate (L.R.) using the following equation: L.R. = Hex[ Int [ 280 / C ] ], where C = ABS [ S1 + S2 + ... + S10 ]. Then, if L.R. < 4, let L.R. = 4, or if L.R. > 255, let L.R. = 255. 6. Set the FIFO Leak Rate Register (address 049H, 079H, 0A9H or 0D9H of each memory group) with the value between 4 and 255 calculated above, then take another one-second sample (e.g., S11). 7. Recalculate the value of 'C' by subtracting the oldest sample and adding the newest, and calculate a new leak rate, as described in Note 5 (e.g., using S2 through S11). 8. Continue to repeat the steps described in Notes 5, 6 and 7 until AIS, LOP LOS or NDF is received or until you reset the , E1Mx16.
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JITTER MEASUREMENTS Equipment used in E1Mx16 jitter measurements: * Hewlett-Packard Digital Transmission Analyzer: * Anritsu Digital Transmission Analyzer: * Anritsu STM/SONET Analyzer: HP-3784A ME520B MP1560A
E1Mx16 TXC-04216
The following table lists the filter characteristics defined by specification: Specifications G.703 Interface 2048 kbit/s Filter Used f1 (High Pass) 20 Hz 20 dB/decade HP1 Filter Characteristics f3 (High Pass) 18 kHz 20 dB/decade HP2 f4 (Low Pass) 100 kHz -20 dB/decade LP
Jitter Tolerance Test The jitter tolerance test is performed by inserting various jitter levels at selected frequencies into the 2.048 Mbit/s line input of the E1Mx16, as shown in the table below and Figure 20. Data is looped back at the SDH/ SONET interface and dropped by the same E1Mx16 device. The measured value is the maximum input jitter that the E1Mx16 can tolerate at its input without generating bit errors in the loopback path. Figure 21 is a plot of the measured data listed in the table together with the requirement.
Input Jitter Frequency 10 Hz 2.4 kHz 18 kHz 100 kHz
Requirement >1.5 UI > 1.5 UI > 0.2 UI > 0.2 UI
Maximum Input Jitter Tolerated (UI-PP) 10 UI 2.3 UI 2.2 UI 1.0 UI
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Figure 18. Jitter Tolerance and Jitter Test Arrangements
E1Mx16 TXC-04216
Receiver External Loopback 155 Mbit/s
E1Mx16 Test Fixture
2.048 Mbit/s E 1 Interface Transmitter
PDH Digital Transmission Analyzer
Figure 19. Jitter Tolerance Measurements with Requirement
10
UI
1
Measured Required (Min)
0.1 10
100 1000 10000 Input Jitter Frequency, Hz
100000
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Jitter Transfer Test
E1Mx16 TXC-04216
A fixed jitter level of 1.0 UI is inserted into the transmitted E1 signal. The jitter value measured is achieved using the HP1/LP filter in the PDH receiver. The jitter transfer measurements are provided in the following table and Figure 20. Input Jitter Frequency 10 Hz 50 Hz 100 Hz 200 Hz 600 Hz 1000 Hz Unit Interval 1.0 UI 1.0 UI 1.0 UI 1.0 UI 1.0 UI 1.0 UI f1-f4 (HP1/LP) Filter Used Jitter Transfer (UI - PP, max) 0.172 UI 0.127 UI 0.117 UI 0.099 UI 0.076 UI 0.075 UI
Figure 20. Jitter Transfer Measurements
10.0
1.0 Input M e as ured 0.1
UI 0.0 10 100 Input Jitte r Fre que ncy 1000
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Mapping Jitter Measurement
E1Mx16 TXC-04216
The following table lists the mapping jitter measurements, which are made with a SDH/SONET Analyzer replacing the 155 Mbit/s loopback in Figure 18.
G.703 Interface 2048 kbit/s
Filter Characteristics f1-f4 (HP1/LP) f3-f4 (HP2/LP)
Maximum Output Jitter (UI-PP) Requirement (Note 1) < 0.075 UI Measured Value 0.032 0.024
Note 1: These values are for further study.
Combined Jitter Measurement The following table lists the combined jitter measurements.
Pointer Test Sequence
Filter
Leak Rate (Hex) (Note 1) 01H 12H 12H 16H
Maximum Output Jitter (UI - PP) Requirement < 0.4 (Note 2) Measured 0.019 0.169 0.169 0.164 < 0.075 (Note 2) 0.009 0.009 0.009 0.009
1 2 3 4 1
Single Pointers of Opposite Polarity Regular Pointers Plus One Double Pointer Regular Pointers with One Missing Pointer Double Pointers of Opposite Polarity Single Pointers of Opposite Polarity Regular Pointers Plus One Double Pointer Regular Pointers with One Missing Pointer Double Pointers of Opposite Polarity
f1-f4 (HP1/LP)
f3-f4 (HP2/LP)
01H 12H 12H 16H
Note 1: These values are written into the Desynchronizer Pointer Leak Rate Register for mapper port n (register address 049, 079, 0A9, 0D9 hex, for n = 1 - 4). Note 2: The limit corresponds to the pointer sequences shown in Figure 21 for Standard Pointer Test Sequences, (T1 > 10 s, T2 > 0.75 s, T3 = 30 ms). The T3 value was constrained by test equipment limitations.
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Figure 21. Standard Pointer Test Sequences
T1 Single Pointers of Opposite Polarity T2 T3
E1Mx16 TXC-04216
Regular Pointers plus one Double Pointer T2
Regular Pointers with one Missing Value T3 T1 Double Pointers of Opposite Polarity
(Ref: ITU-T G.783, Fig 6-2)
T3
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INTERNAL SPOT PROCESSORS
E1Mx16 TXC-04216
The internal SPOT processors of the E1Mx16 device are SONET Processors for Overhead Termination. The purpose of the SPOT processors is to relieve the device's internal logic of the need to support relatively slow functions like performance monitoring and alarm handling. The utility of this feature will grow as communications standards require tighter control of data flow and network management. In addition, as boards become more densely populated with VLSI components, the availability of the SPOT processors will help by reducing the requirement for external components and the workload of the main processor (and the software engineers who program it). Each of the four SPOT processors is a programmable core which adheres to Reduced Instruction Set Computer (RISC) principles. It executes one instruction per clock cycle. Instructions are simple, performing data movement, basic arithmetic functions (8-bit integer operations, but no multiply/divide) and program control. The executable code required for operation of the SPOT processor and associated descriptive text are available as files on a diskette (see Ordering Information section for part number) or via the Products page of the TranSwitch Internet World Wide Web site at www.transwitch.com, where the files are provided in ZIP format. Each SPOT processor is designed to run at 29.16 MHz. This clock is internally derived from the 58.32 MHz desynchronizer clock input (EXTCK). The Instruction RAM (I-RAM) has 2048 words of 16 bits while the Data RAM (D-RAM) has 2048 words of 8 bits. Each SPOT processor has access to the Microprocessor Interface and the Add/Drop Engines of the E1Mx16 via an 8-bit data bus, as shown in Figure 22. Each SPOT processor is event-driven, with each client independently and asynchronously requesting service. These maskable requests are surveyed by a task queue and prioritized by function (Add, Drop, Line). When idle, each SPOT processor polls the task queue to identify the next client to be serviced. This results in a call to the appropriate subroutine(s). During each subroutine, each SPOT processor may transfer data to/from the Add/Drop Engines or the Microprocessor Interface. Each SPOT processor will make decisions regarding control/status and update any necessary counters and other Data RAM locations. The subroutine is terminated by returning to the idle loop, and the cycle is then repeated. The E1 data paths (i.e., for the Add/Drop Engines) are implemented in free-running hardware, and are therefore not dependent on the SPOT processor. The Data RAM contains important information about the status of the E1 channels. Performance counters, J2 messages, etc., are all stored there. The external microprocessor is granted access to the internal Data RAM when addressing the appropriate locations. Since RAM access is arbitrated, the grant will not be immediate, and the RDYp/DTACKp signal is de-asserted until the requested data becomes available. Since each SPOT processor is effectively a very large state machine, it could enter an unforeseen state (e.g., due to a software bug or RAM corruption) which prevents it from servicing all requests in a timely manner. Although the data path is not interrupted, the path overhead bytes may not be correctly processed under these conditions. Two status bits have been provided to detect critical errors which are indications of this status: Parity Error (PERRp) in bit 4 of addresses 028H and 029H of each memory group indicates that a parity error has occurred in reading the Instruction RAM. Watchdog Timer Expired (WDTEXPp) in bit 6 of addresses 028H and 029H of each memory group indicates that the SPOT processor may be unable to service all requests in a timely manner. Some possible causes for this condition are excessive microprocessor accesses, a SPOT processor clock that is running too slowly, or a software bug.
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E1Mx16 TXC-04216
Upon power-up or hardware reset, the contents of the Instruction RAM are assumed to be invalid and execution of the SPOT program is internally disabled. Before a SPOT processor can begin processing, the microprocessor must reprogram the Instruction RAM, using the instructions described in the following table, by performing the procedure described in the flowchart in Figure 23. Each of the four SPOT processors is selected by placing a low on the microprocessor bus interface lead SELp (p=1-4). Each of the four SPOT processors must be programmed using the procedure following the table below. Table 1: Reprogram Functions (valid only when control bit RPSPOTp at bit 7 in address 007H is a 1) Function wrPC rdPC0 rdPC1 IRAMwr IRAMrd Direction write read read write read Microprocessor Interface Address* 102H 102H 103H 100H 100H Description IRAMptr <== SPOTPCLDp(10-0) read IRAMptr[7:0] read IRAMptr[10:8] *IRAMptr++ <== data data <== *IRAMptr++
*Note: Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
The 11-bit SPOT PC Load register SPOTPCLDp at address 007H bits 2-0 of each memory group and address 006H bits 7-0 of each memory group is first initialized. This is an offset address into the Instruction RAM. It may not be necessary always to write/read the entire program, but for normal operation this register should be set to 000H. In order to access the Instruction RAM, set to 1 the Reprogram SPOT control bit RPSPOTp at bit 7 in address 007H of each memory group. At this time the Data RAM is off-line (i.e., it is inaccessible to the microprocessor), but all register-based locations are still available. SPOT program execution is disabled when RPSPOTp is a 1. Function "wrPC" causes the Instruction RAM word pointer to be loaded from the SPOT PC Load register. Each SPOT processor automatically increments the Instruction RAM word pointer, which allows the microprocessor to write all instructions to one address (100H). Since the length of the Instruction RAM is 2048 16-bit words, 4096 IRAM 8-bit write functions ("IRAMwr") are required to program a SPOT processor completely. Transwitch provides the 4096 bytes of code that will implement the features mentioned in this document. It is recommended, but not required, that the writes to the Instruction RAM should be verified as part of the initialization procedure. As shown in the flowchart, it is necessary only to use the instruction "wrPC" to reload the I-RAM word pointer and then perform 4096 I-RAM read cycles using the same fixed data location (100H) as that used for write (function "IRAMrd"). The programming procedure is completed by setting control bit RPSPOTp to 0. At this point, the word pointer is reloaded and execution of the SPOT processor program execution is enabled. It is important to set control bit INITSPp at address 015H, bit 0 to 1 at some time after programming each SPOT processor. This will cause each SPOT processor to execute an initialization subroutine from the Instruction RAM that will initialize the Data RAM and reset its general purpose registers to allow other subroutines to begin running from a known state.
Note: Programming may be performed in parallel for the four SPOT processors, but verification must be performed on each SPOT processor individually.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Figure 22. Schematic Diagram of E1Mx16 Showing SPOT Processor Interfaces SDH/SONET SIDE DROP Engine Drop[A] LINE SIDE
Rx Port
Drop[B]
Inst. RAM
Data RAM
arbiter
RAM I/F Control/Status P I/O
SPOT
P Interface
ADD Engine Add[A]
Tx Port
Add[B]
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Figure 23. Recommended Implementation Flowchart for Reprogramming the SPOT Processor
Initialize LATENp = 0 HDWIEp = 1 SPTMSKp = 1 SPOTPCLDp=000H RPSPOTp = 1
wrPC 102H = 00H
Download
Write next byte No more data? n 100H = data
y
wrPC 102H = 00H
Verify
Read next byte No more data? n data = 100H
y
Wrap Up RPSPOTp = 0
Note: RESTSPp must be 0 during reprogramming.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
BOUNDARY SCAN Introduction
E1Mx16 TXC-04216
The Boundary Scan Interface Block provide a five-lead Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external I/O leads from the TAP for board and component test. The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. As shown in Figure 24, one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is shown in Figure 14. The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. Detailed information on the operation of this state machine can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. These three serial registers are connected in parallel between the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 24. The boundary scan function can be reset and disabled by holding lead TRS low. When boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the E1Mx16 device's internal logic. During boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. Boundary Scan Operation The maximum frequency the E1Mx16 device will support for boundary scan is 10 MHz. The timing diagrams for the boundary scan interface leads are shown in Figure 14. The instruction register contains twelve bits. The E1Mx16 device performs the following three boundary scan test instructions: The EXTEST test instruction (000000000000) provides the ability to test the connectivity of the E1Mx16 device to external circuitry. The SAMPLE test instruction (010010010010) provides the ability to examine the boundary scan register contents without interfering with device operation. The BYPASS test instruction (111111111111) provides the ability to bypass the E1Mx16 boundary scan and instruction registers.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Boundary Scan Reset
E1Mx16 TXC-04216
Specific control of the TRS lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. This lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the Test Access Port (TAP) controller during power-up of the E1Mx16. If boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the VIL requirements listed in the `Input, Output and Input/Output Parameters' section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor.
Boundary Scan Register
CORE LOGIC 2
CORE LOGIC 3
Instruction Register Bypass Register TAP Controller
Instruction Register Bypass Register TAP Controller
Signal input and output leads (solder balls on bottom surface of PBGA package)
CORE LOGIC 1
CORE LOGIC 4
Instruction Register Bypass Register TAP Controller
Instruction Register Bypass Register TAP Controller
TDI
TDO
3 TCK TMS TRS IN Controls OUT
Boundary Scan Serial Test Data
Figure 24. Boundary Scan Schematic
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Boundary Scan Chain
E1Mx16 TXC-04216
The E1Mx16 contains four identical QE1M VLSI chips, each of which has its own boundary scan chain. Since these chips drive common input and output leads, it is not feasible to develop a BSDL file for the overall device. Instead, to facilitate customer testing of the E1Mx16, TranSwitch has developed a module-level test approach that utilizes a device net list1 (prepared in a Teradyne tester format) and the BSDL2 file for the QE1M, modified to suit the E1Mx16 application. The associated files and explanatory material are combined in a .ZIP file format. This file, together with other E1Mx16 product documentation, is available on the TranSwitch Internet Web site (www.transwitch.com). It can be located by using the "Product Finder" segment on the Home page to select Product Name E1Mx16, or by entering E1Mx16 in the Search box and selecting the first response.
MULTIPLEX FORMAT AND MAPPING INFORMATION STS-1 VT2 (2.048 Mbit/s) Multiplex Format Mapping The following diagram and table illustrate the mapping of the 21 VT2s into an STS-1 SPE. Column 1 is assigned to carry the path overhead bytes.
VT2
4 COLUMNS
1 2 3
1 5
2
3
4
36
36
1 J1 B3 C2 VT 2 G1 # F2 1 H4 Z3 Z4 Z5 2 23 VT 2 # 2 VT 2 # 21 VT 2 # 1 VT 2 # 2 R R R R R R R R R 30 45 VT 2 # 21 VT 2 # 1 VT 2 # 2 R R R R R R R R R 59 67 87 VT 2 # 21 VT 2 # 1 VT 2 # 21
1. The net list is a text file that describes the interconnections of the four chips within the device and their connections to the E1Mx16 package leads. 2. The Boundary Scan Description Language (BSDL) file describes the Boundary Scan Chain for the silicon chip of the E1Mx16 device. This must be used four times to provide complete coverage of all Boundary Scan cells in the E1Mx16. - 88 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
STS-1 Mapping (2.048 Mbit/s) RTUNnp, TTUNnp Locations1 04CH, 04DH Port 1 0ACH, 0ADH Port 3 07CH, 07DH Port 2 0DCH, 0DDH Port 4 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Notes: 1. Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16. 2. Columns 30 and 59 carry fixed stuff bytes. Column 1 is assigned for the POH bytes.
E1Mx16 TXC-04216
VT#
VT2 Column Numbers2
5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1
3 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1
2 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 No VT Selected 2, 23, 45, 67 3, 24, 46, 68 4, 25, 47, 69 5, 26, 48, 70 6, 27, 49, 71 7, 28, 50, 72 8, 29, 51, 73 9, 31, 52, 74 10, 32, 53, 75 11, 33, 54, 76 12, 34, 55, 77 13, 35, 56, 78 14, 36, 57, 79 15, 37, 58, 80 16, 38, 60, 81 17, 39, 61, 82 18, 40, 62, 83 19, 41, 63, 84 20, 42, 64, 85 21, 43, 65, 86 22, 44, 66, 87
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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DATA SHEET
STS-3/AU-3 VT2/TU-12 (2.048 Mbit/s) Multiplex Format Mapping
E1Mx16 TXC-04216
The following diagram and table illustrate the mapping of the 63 VT2/TU-12s into an STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes.
VT2
4 COLUMNS
1 2 3
36 BYTES
1 5
2
3
4
36
35 36
1 J1 B3 C2 VT 2 G1 # 1 F2 H4 Z3 Z4 Z5
23
29 30 R R VT R 2 #R 7R R R R R
44 45
59 60 R R
66 67
87
1 J1 B3 C2 VT 2 G1 # 22 F2 H4 Z3 Z4 Z5
87
1 J1 B3 C2 VT 2 G1 # 43 F2 H4 Z3 Z4 Z5
87
VT 2 # 1
VT 2 # 21
VT 2 # 1
R VT 2 R# 15 R R R R R
VT VT 22 ## 21 1
VT 2 # 21
VT 2 # 23
VT 2 # 42
VT 2 # 44
VT 2 # 63
1
STS-3/AU-3 SPE
261
Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
STS-3/AU-3 Mapping (2.048 Mbit/s)
RTUNnp, TTUNnp 04CH, 04DH Port 1 TU/ 07CH, 07DH Port 2 VT 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers1 6543210 0000000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0100101 0101001 0101101 0110001 0110101 0111001 0111101 0100110 0101010 0101110 0110010 0110110 0111010 0111110 0100111 0101011 0101111 0110011 0110111 0111011 0111111 4, 67, 133, 199 7, 70, 136, 202 10, 73, 139, 205 13, 76, 142, 208 16, 79, 145, 211 19, 82, 148, 214 22, 85, 151, 217 25, 91, 154, 220 28, 94, 157, 223 31, 97, 160, 226 34, 100, 163, 229 37, 103, 166, 232 40, 106, 169, 235 43, 109, 172, 238 46, 112, 178, 241 49, 115, 181, 244 52, 118, 184, 247 55, 121, 187, 250 58, 124, 190, 253 61, 127, 193, 256 64, 130, 196, 259 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1000101 1001001 1001101 1010001 1010101 1011001 1011101 1000110 1001010 1001110 1010010 1010110 1011010 1011110 1000111 1001011 1001111 1010011 1010111 1011011 1011111 RTUNnp, TTUNnp 04CH, 04DH Port 1 TU/ 07CH, 07DH Port 2 VT 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers1 6543210 RTUNnp, TTUNnp 04CH, 04DH Port 1 TU/ 07CH, 07DH Port 2 VT 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers1 6543210
E1Mx16 TXC-04216
STS-3/AU-3 Column Numbers2
STS-3/AU-3 Column Numbers2
STS-3/AU-3 Column Numbers2
No TU/VT Selected 5, 68, 134, 200 8, 71, 137, 203 11, 74, 140, 206 14, 77, 143, 209 17, 80, 146, 212 20, 83, 149, 215 23, 86, 152, 218 26, 92, 155, 221 29, 95, 158, 224 32, 98, 161, 227 35, 101, 164, 230 38, 104, 167, 233 41, 107, 170, 236 44, 110, 173, 239 47, 113, 179, 242 50, 116, 182, 245 53, 119, 185, 248 56, 122, 188, 251 59, 125, 191, 254 62, 128, 194, 257 65, 131, 197, 260 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1100101 1101001 1101101 1110001 1110101 1111001 1111101 1100110 1101010 1101110 1110010 1110110 1111010 1111110 1100111 1101011 1101111 1110011 1110111 1111011 1111111 6, 69, 135, 201 9, 72, 138, 204 12, 75, 141, 207 15, 78, 144, 210 18, 81, 147, 213 21, 84, 150, 216 24, 87, 153, 219 27, 93, 156, 222 30, 96, 159, 225 33, 99, 162, 228 36, 102, 165, 231 39, 105, 168, 234 42, 108, 171, 237 45, 111, 174, 240 48, 114, 180, 243 51, 117, 183, 246 54, 120, 186, 249 57, 123, 189, 252 60, 126, 192, 255 63, 129, 195, 258 66, 132, 198, 261
STS-1 #1, AU-3 A
STS-1 #2, AU-3 B
STS-1 #3, AU-3 C
Notes: 1. Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16. 2. Columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
STM-1/VC-4 TU-12 (2048 kbit/s) Multiplex Format Mapping
E1Mx16 TXC-04216
The following diagram and table illustrate the mapping of the 63 TU-12s into an STM-1/VC-4. The E1Mx16 provides control bits for enabling the Null Pointer Indicators (NPIs) for the columns indicated.
4 COLUMNS
1 2 3
1 5
2
3
4
TU-12 #1
36
36
1 2 3 TUG-2 #1
1 2 3
1 2 3
1 2 3
1 N P I
3
24
45
66
86
1 N P I
86
1 N P I
86
1
7
1
71
7
1
7
8
14
15
21
TUG-3A
TUG-3B
TUG-3C
VC-4 P O H
1
STM-1/VC-4
261
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
STM-1 VC-4 Mode (2048 kbit/s)
RTUNnp, TTUNnp 04CH, 04DH Port 1 07CH, 07DH Port 2 TU 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers* 6543210 0000000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0100101 0101001 0101101 0110001 0110101 0111001 0111101 0100110 0101010 0101110 0110010 0110110 0111010 0111110 0100111 0101011 0101111 0110011 0110111 0111011 0111111 10, 73, 136, 199 13, 76, 139, 202 16, 79, 142, 205 19, 82, 145, 208 22, 85, 148, 211 25, 88, 151, 214 28, 91, 154, 217 31, 94, 157, 220 34, 97, 160, 223 37, 100, 163, 226 40, 103, 166, 229 43, 106, 169, 232 46, 109, 172, 235 49, 112, 175, 238 52, 115, 178, 241 55, 118, 181, 244 58, 121, 184, 247 61, 124, 187, 250 64, 127, 190, 253 67, 130, 193, 256 70, 133, 196, 259 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1000101 1001001 1001101 1010001 1010101 1011001 1011101 1000110 1001010 1001110 1010010 1010110 1011010 1011110 1000111 1001011 1001111 1010011 1010111 1011011 1011111 RTUNnp, TTUNnp 04CH, 04DH Port 1 07CH, 07DH Port 2 TU 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers* 6543210 RTUNnp, TTUNnp 04CH, 04DH Port 1 07CH, 07DH Port 2 TU 0ACH, 0ADH Port 3 # 0DCH, 0DDH Port 4 Registers* 6543210
E1Mx16 TXC-04216
VC-4 Column Numbers
VC-4 Column Numbers
VC-4 Column Numbers
No TU Selected 11, 74, 137, 200 14, 77, 140, 203 17, 80, 143, 206 20, 83, 146, 209 23, 86, 149, 212 26, 89, 152, 215 29, 92, 155, 218 32, 95, 158, 221 35, 98, 161, 224 38, 101, 164, 227 41, 104, 167, 230 44, 107, 170, 233 47, 110, 173, 236 50, 113, 176, 239 53, 116, 179, 242 56, 119, 182, 245 59, 122, 185, 248 62, 125, 188, 251 65, 128, 191, 254 68, 131, 194, 257 71, 134, 197, 260 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1100101 1101001 1101101 1110001 1110101 1111001 1111101 1100110 1101010 1101110 1110010 1110110 1111010 1111110 1100111 1101011 1101111 1110011 1110111 1111011 1111111 12, 75, 138, 201 15, 78, 141, 204 18, 81, 144, 207 21, 84, 147, 210 24, 87, 150, 213 27, 90, 153, 216 30, 93, 156, 219 33, 96, 159, 222 36, 99, 162, 225 39, 102, 165, 228 42, 105, 168, 231 45, 108, 171, 234 48, 111, 174, 237 51, 114, 177, 240 54, 117, 180, 243 57, 120, 183, 246 60, 123, 186, 249 63, 126, 189, 252 66, 129, 192, 255 69, 132, 195, 258 72, 135, 198, 261
*Note: Address map locations represent each of the mapper groups p (p=1-4) in the E1Mx16.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET MEMORY MAP
E1Mx16 TXC-04216
The E1Mx16 memory map consists of counters and register bit positions which may be accessed by the microprocessor. There are 4 common groups that provide control and status bits common to groups of 4 mapper channels each and 16 individual channel groups that provide the control and status bits for each mapper channel. These four groups are selected by placing a low on the microprocessor bus interface leads SELp (p=1-4). The group is selected by SELp, where p selects the group of channels (p=1 selects channels 1-4, p=2 selects channels 5-8, p=3 selects channels 9-12 and p=4 selects channels 13-16).The memory map segment consists of 7FF (hex) address locations for each of the four groups. Address locations in the range 000H - 7FFH that are shown as unused, or are unlisted, must not be accessed by the microprocessor. Unused bit positions within register locations will contain unspecified values when read, unless a 0 or 1 value is indicated in the tables below, or the address can be written by the microprocessor, in which case unused bit positions must always be set to 0. All counters saturate at full count and are cleared when they are read. The 4 common groups should be set to the same values for p=1-4. The 16 individual channel groups may be independently set and the 16 TU/VT select locations must be set to different values for proper operation. The common memory map segment consists of the Device ID, Program ID, Internal Processor, Control, Provisioning, Interrupt Indication, and Interrupt Status registers. The A bus segment consists of the A Drop and Add status registers. The B bus segment consists of the B Drop and Add status registers. Each Port n memory map segment (where n = 1-4) consists of the Desynchronizer, Provisioning, Status and Operations registers, and various counters. There are also Port n registers for J2 and N2 (Z6) message segments. n = 1-4 corresponds to the four channels of the parent group. Some memory locations, at addresses 032H and above, are shown shaded in the memory map. These locations reside in the 2k x 8 Data RAM of the internal SPOT processors and are not reset by the software or hardware resets but only by INITSPp. They are subject to arbitrated access by both the internal SPOT processors and the external microprocessor. An attempt to access any of these locations will toggle the RDYp/DTACKp output lead to pause the external microprocessor until the location is available for external access. While control bit RPSPOTp is set to 1, these locations are assigned to use by the associated SPOT processor and must not be accessed by the external microprocessor unless they are addresses designated for microprocessor access while the SPOT processor is being reprogrammed (i.e., addresses 100H, 102H and 103H). Refer to Figures 10 through 13 and the notes associated with these figures for more information. DEVICE ID Address Status* (Hex) 000 001 002 003 004 R R R R R Bit 7 1 1 0 Bit 6 1 1 0 Bit 5 0 0 0 Bit 4 1 0 0 Bit 3 0 0 1 0 Bit 2 1 0 0 0 Bit 1 1 0 0 0 Bit 0 1 0 1 1
Revision (Version) Level Mask Level (reads as 0000)
Growth (reads as 0000)
PROGRAM ID (p=1-4) Address Status* (Hex) 6BD 6BE 6BF R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Program Revision Checksum/execution flag (PID-CHKp) Part 1 of two-part program release number (PGMRV1p) Part 2 of two-part program release number (PGMRV2p)
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
INTERNAL PROCESSOR SPOT (p=1-4)) Address Status* (Hex) 005 006 007 008 R/W R/W R/W R/W
RPSPOTp
E1Mx16 TXC-04216
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TranSwitch Test Register(p) - (set to 00H) SPOTPCLDp (7 - 0) TranSwitch Test Bits(p) - (set to 0000) SPOTPCLDp (10 - 8) TranSwitch Test Register(p) - (set to 00H)
COMMON REGISTERS - CONTROLS (p=1-4) Address Status* (Hex) 010 011 012 013 R/W R/W R/W R/W Bit 7 MOD1p SBTENp ADDIp Bit 6 MOD0p DRPBTp APEp Bit 5 AAHZEp ABDp IPOSp Bit 4 BAHZEp LATENp INEGp Bit 3 BLOCKp TAISEp RFIEp NULLZp Bit 2 NPIAp TCLKIp
THRSBYp
Bit 1 NPIBp RAISEp DPEp UQAEp
Bit 0 NPICp RCLKIp PDDOp TOBWZp
HEAISEp DV1SELp DV1REFp RDIENp
DDINDp
COMMON REGISTERS - PROVISIONING CONTROL (p=1-4)) Address Status* (Hex) 014 015 0F1 0F5 R/W W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HDWIEp
INITSPp
Unused(p) - (set to 000) 0 TxB2DISp 0 0 0 0
UEAMEp SE1AISp V5AL10p PTALTEp Unused(p) - (set to 000) V4ENp 0 0 0 0 0 0 0
RESETp RESTABp RESTBBp RESTSPp
0 0
COMMON REGISTERS - INTERRUPT INDICATION (p=1-4) Address Status* (Hex) 020 R Bit 7 INTp Bit 6 EXTCKp Bit 5 ASIDEp Bit 4 BSIDEp Bit 3 PORT4p Bit 2 PORT3p Bit 1 PORT2p Bit 0 PORT1p
COMMON REGISTERS - INTERRUPT MASK (p=1-4) Address Status* (Hex) 016 017 018 019 021 R/W R/W R/W R/W R/W Bit 7 0 RPT4Ap
TPORT4p
Bit 6 0 RPT4Bp
TPORT3p
Bit 5 0 RPT3Ap
TPORT2p
Bit 4 0 RPT3Bp
TPORT1p
Bit 3 0 RPT2Ap
RFIFO4p
Bit 2 0 RPT2Bp
RFIFO3p
Bit 1 0 RPT1Ap
RFIFO2p
Bit 0
SPTMSKp
RPT1Bp
RFIFO1p
TFIFO4Ap TFIFO4Bp TFIFO3Ap TFIFO3Bp TFIFO2Ap TFIFO2Bp TFIFO1Ap TFIFO1Bp
0
ECKMSKp ASMSKp
BSMSKp
P4MSKp
P3MSKp
P2MSKp
P1MSKp
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
A/B DROP AND ADD BUS REGISTERS - DESYNCHRONIZER AND INTERNAL PROCESSOR (SPOT) STATUS (p=1-4) Address Status* (Hex) 022 023 024 025 026 027 028 029 R(L) R R(L) R R(L) R R(L) R Bit 7 Bit 6 Bit 5 ADPARp ADPARp 0 0 BDPARp BDPARp 0 0 Bit 4 0 0 0 0 0 0 PERRp PERRp Bit 3 0 0 0 0 0 0 0 0 Bit 2 Bit 1 Bit 0
ADLOCp AALOCp ADLOCp AALOCp LEXTCp LEXTCp 0 0
A3UAISIp A2UAISIp A1UAISIp A3UAISIp A2UAISIp A1UAISIp A3DH4Ep A2DH4Ep A1DH4Ep A3DH4Ep A2DH4Ep A1DH4Ep B3UAISIp B2UAISIp B1UAISIp B3UAISIp B2UAISIp B1UAISIp B3DH4Ep B2DH4Ep B1DH4Ep B3DH4Ep B2DH4Ep B1DH4Ep
BDLOCp BALOCp BDLOCp BALOCp
SPTLOCp WDTEXPp SPTLOCp WDTEXPp
DESYNCHRONIZER CONTROL - PORT n (p=1-4) Address Port 1, 2, 3, 4
049 079 0A9 0D9
Status* R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Desynchronizer Pointer Leak Rate Register(np)
PROVISIONING (CONTROL) - PORT n (p=1-4) Address Port 1, 2, 3, 4
04A 07A 0AA 0DA 04B 07B 0AB 0DB 04C 07C 0AC 0DC 04D 07D 0AD 0DD
Status* R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 RnENp
Bit 0 0
TnSEL1p TnSEL0p RnSELp UCHnEp USCHnEp BYPASnp 0 0 Receive TU/VT Select - (RTUNnp) Transmit TU/VT Select - (TTUNnp)
ADnENp BDnENp AAnENp BAnENp ANAnTxp ANAnENp PRBSnENp FRDISnp
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
STATUS REGISTERS AND COUNTERS - PORT n (A SIDE) (p=1-4) Address Port 1, 2, 3, 4
030 060 090 0C0 031 061 091 0C1 032 062 092 0C2 033 063 093 0C3 034 064 094 0C4 035 065 095 0C5 04E 07E 0AE 0DE 04F 07F 0AF 0DF 036 066 096 0C6 037 067 097 0C7 038 068 098 0C8 039 069 099 0C9 05A 08A 0BA 0EA 05B 08B 0BB 0EB 100 200 300 400 101 201 301 401 102 202 302 402 116 216 316 416
E1Mx16 TXC-04216
Status* R(L) R R R R R R(L) R R R R R R(L) R R R R R
Bit 7 AnAISp AnAISp
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AnLOPp AnSIZEp AnNDFp AnRDISp AnRFIp AnUNEQp AnSLERp AnLOPp AnSIZEp AnNDFp AnRDISp AnRFIp AnUNEQp AnSLERp AnPJ Counter(p) AnBIP2 Error Counter(p) AnFEBE Counter(p) Unused(np) An Rx Label(p)
AnJ2LOLp AnJ2TIMp AnJ2LOLp AnJ2TIMp
AnNJ Counter(p)
AnRDIPp AnRDICp AnRDIPp AnRDICp
Unused(np) (00) Unused(np) (00)
Unused(np) (00) Unused(np) (00)
Unused(np) Unused(np) An Receive K4 (Z7) Byte(p) An Receive O-Bits(p)
AnTCUQp AnTCAISp AnTCLMp AnTCLLp AnTCTMp AnTCODIp AnTCRDIp AnTCUQp AnTCAISp AnTCLMp AnTCLLp AnTCTMp AnTCODIp AnTCRDIp
0 0
An TC BIP-2 Error Counter(p) An TC REI Counter(p) An TC OEI Counter(p) An Receive V4 Byte(p)
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
RECEIVE STATUS REGISTERS AND COUNTERS - PORT n (B SIDE) (p=1-4) Address Port 1, 2, 3, 4
03A 06A 09A 0CA 03B 06B 09B 0CB 03C 06C 09C 0CC 03D 06D 09D 0CD 03E 06E 09E 0CE 03F 06F 09F 0CF 05E 08E 0BE 0EE 05F 08F 0BF 0EF 040 070 0A0 0D0 041 071 0A1 0D1 042 072 0A2 0D2 043 073 0A3 0D3 05C 08C 0BC 0EC 05D 08D 0BD 0ED 180 280 380 480 181 281 381 481 182 282 382 482 196 296 396 496
E1Mx16 TXC-04216
Status* R(L) R R R R R R(L) R R R R R R(L) R R R R R
Bit 7 BnAISp BnAISp
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BnLOPp BnSIZEp BnNDFp BnRDISp BnRFIp BnUNEQp BnSLERp BnLOPp BnSIZEp BnNDFp BnRDISp BnRFIp BnUNEQp BnSLERp BnPJ Counter(p) BnBIP2 Error Counter(p) BnFEBE Counter(p) Unused(np) Bn Rx Label(p)
BnJ2LOLp BnJ2TIMp BnJ2LOLp BnJ2TIMp
BnNJ Counter(p)
BnRDIPp BnRDICp BnRDIPp BnRDICp
Unused(np) (00) Unused(np) (00)
Unused(np) (00) Unused(np) (00)
Unused(np) Unused(np) Bn Receive K4 (Z7) Byte(p) Bn Receive O-Bits(p)
BnTCUQp BnTCAISp BnTCLMp BnTCLLp BnTCTMp BnTCODIp BnTCRDIp BnTCUQp BnTCAISp BnTCLMp BnTCLLp BnTCTMp BnTCODIp BnTCRDIp
0 0
Bn TC BIP-2 Error Counter(p) Bn TC REI Counter(p) Bn TC OEI Counter(p) Bn Receive V4 Byte(p)
STATUS REGISTERS - PORT n (A AND B SIDES) (p=1-4) Address Port 1, 2, 3, 4
044 074 0A4 0D4 045 075 0A5 0D5 046 076 0A6 0D6 047 077 0A7 0D7
Status* R(L) R R R
Bit 7 RnFFEp RnFFEp
Bit 6 0 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANAnOOLp TAnFEp ANAnOOLp TAnFEp
TBnFEp TnLOSp TnLOCp TnDAISp TBnFEp TnLOSp TnLOCp TnDAISp
Port n HDB3 Coding Errors(p) (Low Byte) Port n HDB3 Coding Errors(p) (High Byte)
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
OPERATIONS (CONTROL) REGISTERS - PORT n (p=1-4) Address Port 1, 2, 3, 4
048 078 0A8 0D8 050 080 0B0 0E0 051 081 0B1 0E1 052 082 0B2 0E2 053 083 0B3 0E3 054 084 0B4 0E4 055 085 0B5 0E5 056 086 0B6 0E6 057 087 0B7 0E7 058 088 0B8 0E8 059 089 0B9 0E9 511 591 611 691
E1Mx16 TXC-04216
Status* R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused(np) (set to 000) FnLBKp LnLBKp RnAISp
1BnRDIp J2nTENp J2nSIZEp J2nCOMp J2nAISEp TnAISp
TnVTAISp
TnRFIp TnRDISp TnRDIPp TnFB2p TnFFBp
TCnRDIp TCnODIp TCnAISp TCnENp TCnREp TCnOEp TCnAENp TnRDICp
RnSETSp RnSETCp
Unused(np) (set to 0000)
Unused(np) (set to 00000) Unused(np) (set to 00000) Unused(np) (set to 00000) Unused(np) Unused(np) Transmit K4 (Z7) Byte Value(np) (4-7)
An P Mismatch Label(p) Bn P Mismatch Label(p) Tn TX Label(p)
Unused(np) - (set to 000)
TZ7BVnp(0)
Transmit O-Bits(p) - Port n Transmit V4 Bytes(p) - Port n
J2 AND N2 (Z6) MESSAGE SEGMENTS - PORT n (p=1-4) Address Port 1, 2, 3, 4 140 240 340 440 to 17F 27F 37F 47F Status* R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port n Group p A side J2 64-byte trace message received (X40 - X7F) or A side J2 16-byte trace message received (X40 - X4F) A side J2 16-byte microprocessor-written trace message (X50 - X5F) A side TC (N2 (Z6)) 16-byte trace message received (X60 - X6F) A side TC (N2 (Z6)) 16-byte microprocessor-written trace message (X70 - X7F) Port n Group p B side J2 64-byte trace message received (XC0 - XFF) or B side J2 16-byte trace message received (XC0 - XCF) B side J2 16-byte microprocessor-written trace message (XD0 - XDF) B side TC (N2 (Z6)) 16-byte trace message received (XE0 - XEF) B side TC (N2 (Z6)) 16-byte microprocessor-written trace message (XF0 - XFF) Port n Group p J2 64-byte trace message transmitted (540 - 57F Port 1, 5C0 - 5FF Port 2, 640 - 67F Port 3, 6C0 - 6FF Port 4) or J2 16-byte trace message transmitted (540-54F Port 1, 5C0-5CF Port 2, 640-64F Port 3, 6C0-6CF Port 4) TC (N2 (Z6)) 16-byte trace message transmitted (560-56F Port 1, 5E0-5EF Port 2, 660-66F Port 3, 6E0-6EF Port 4)
1C0 2C0 3C0 4C0 to 1FF 2FF 3FF 4FF
R/W
540 5C0 640 6C0 to 57F 5FF 67F 6FF
R/W
Where X = 1 for Port 1, 2 for Port 2, 3 for Port 3, 4 for Port 4. * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET MEMORY MAP DESCRIPTIONS
COMMON REGISTERS - PROGRAM ID (p=1-4) Address 6BD Bit 7-0 Symbol PID-CHKp Description
E1Mx16 TXC-04216
This value (register 6BEH + register 6BFH + 55 hex) is written by SPOT during initialization, and at the start of each maintenance cycle (2 kHz rate). The external microprocessor can read this checksum to validate the revision numbers in registers 6BEH and 6BFH. By writing this location with a different value, waiting at least 1 ms, and then reading this location, the external microprocessor can determine whether the SPOT program is running.
6BE 6BF
7-0 7-0
PGMRV1p* Part 1 of two-part program release number. PGMRV2p* Part 2 of two-part program release number.
* Registers 6BEH and 6BFH contain the two-part SPOT program release number. In documentation, this number is written as "PGMRV1p, PGMRV2p".
COMMON REGISTERS - INTERNAL PROCESSOR (SPOT (p=1-4)) Address 005 006 Bit 7-0 7-0 Symbol Description TranSwitch Test Register: These bits must be written to 0.
SPOTPCLDp Internal SPOT Processor Load Register: These bits are the lower 8 (7-0) bits of the 11-bit register which is used as the offset address access for
the SPOT Instruction RAM. During normal operation these bits must be written to 0. 007 7 RPSPOTp Reprogram Internal SPOT Processor Control Bit: This bit is written to 1 for accessing the SPOT Instruction RAM. During normal operation this bit must be written to 0. TranSwitch Test Bits: These bits must be written to 0.
SPOTPCLDp Internal SPOT Processor Load Register: These bits are the upper 3
6-3 2-0 (10-8)
bits of the 11-bit register which is used as the offset address access for the SPOT Instruction RAM. During normal operation these bits must be written to 0. TranSwitch Test Register: These bits must be written to 0.
008
7-0
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
COMMON REGISTERS - CONTROL DESCRIPTIONS (p=1-4) Address 010 Bit 7 6 Symbol MOD1p MOD0p Description
E1Mx16 TXC-04216
Format Selection: The format selection is made according to the table given below. MOD1p MOD0p Format Selected 0 0 STS-1 Format 0 1 STS-3 Format 1 0 STM-1/AU-3 Format 1 1 STM-1/TUG-3/VC-4 Format
5
AAHZEp
A Add Bus High Impedance Enable: A 1 forces the A-side add bus data output to a high impedance state. Upon power-up, or on a hardware or software reset, this bit is set to a 1. Note: For normal bus operation this bit position must be written with a 0. See Note 1. B Add Bus High Impedance Enable: A 1 forces the B-side add bus data output to a high impedance state. Upon power-up, or on a hardware or software reset, this bit is set to a 1. Note: For normal bus operation this bit position must be written with a 0. See Note 1 Block Count: A 1 enables two BIP-2 errors to be counted as a single error (block) for the BIP-2 performance counters (V5 and K4 (Z7) bytes). A 0 enables two BIP-2 errors to be counted as two errors. Null Pointer Indicator Selection: A 1 enables a null pointer indicator to be generated for the corresponding TUG-3 when control bits MOD1p and MOD0p are a 1 (STM-1/TUG-3/VC-4 format). A null pointer indicator is carried in the first three bytes of column 1 in a TUG-3. The null pointer indicator byte values are 93H, E0H and 00H. A 0 forces the NPI byte position to a high impedance state on the A/B buses.
4
BAHZEp
3
BLOCKp
2 1 0
NPIAp NPIBp NPICp
Note 1:The add bus will be forced to a high impedance state automatically when loss of clock is detected on the transmit clock signal selected by control bit DRPBTp in register 011H.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 011 Bit 7 Symbol SBTENp Description
E1Mx16 TXC-04216
Software Bus Timing Enable: This bit works in conjunction with control bit DRPBTp in bit 6 and the ABUST lead according to the following table (where X = Don't Care): SBTENp DRPBTp ABUST 0 X Low Action Add bus timing selected. Add bus data derived from add bus timing signals. Software control of bus timing disabled. Drop bus timing selected. Add bus data derived from like-named drop bus. Software control of bus timing disabled. Add bus timing selected. Add bus data derived from add bus timing signals. Hardware control of bus timing disabled. Drop bus timing selected. Add bus data derived from like-named drop bus. Hardware control of bus timing disabled.
0
X
High
1
0
X
1
1
X
This SBTENp bit is reset to 0 upon power-up and by a device reset. 6 DRPBTp Drop Bus Timing: Enabled when a 1 is written to control bit SBTENp. A 1 selects the drop bus timing mode, while a 0 selects the add bus timing mode. See table above. Add Bus Delay: A 0 delays the add bus data with respect to the drop bus by one clock cycle, when the drop bus or add bus timing modes are selected. A 1 delays the add bus data with respect to the drop bus or add bus by one additional clock cycle, for a total of two clock cycles. Latch On Transitions Enable Bit: A 0 disables the states of the IPOSp and INEGp control bits, and causes the event alarm bits (latched alarm bits in the registers) to latch on the positive (1) level of an alarm. A 1 enables the states of the IPOSp and INEGp control bits in register 012H. Transmit E1 Line AIS Enable: A common control for all four ports. A 1 enables an E1 AIS (unframed all ones) to be generated and sent from port n to the SDH/SONET side when an E1 line input loss of signal, or loss of clock, occurs for port n. Transmit E1 Line Clock Inversion: A common control for the four ports. A 0 enables transmit data to be clocked in on the negative (falling) clock edges. A 1 enables transmit data to be clocked in on the positive (rising) clock edges.
5
ABDp
4
LATENp
3
TAISEp
2
TCLKIp
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 011 (cont.) Bit 1 Symbol RAISEp Description
E1Mx16 TXC-04216
Receive E1 Line AIS Enable: A common control for the four ports. A 1 enables a receive E1 AIS to be sent from port n when internal defined alarms occur for a port n. An E1 AIS is an unframed all ones signal. For example, receive AIS for port 1 will be generated:
- When R1SELp is 0 and any of: - Loss of pointer detected (A1LOPp) - VT AIS detected (A1AISp) - A Drop Bus Loss Of Clock (ADLOCp) - A Drop Bus Upstream AIS detected (AsUAISIp) when HEAISEp is 1. - or when R1SELp is 0 and RAISEp is 1 (drop VT from A side) and any of: - A Drop H4 Error (AsDH4Ep) when DV1SELp is 0 - Unequipped signal label (A1UNEQp) and UQAEp is 1 - Mismatch signal label (A1SLERp) - J2 Loss Of Lock Alarm (A1J2LOLp) when J21COMp and J21AISEp are 1, and J21SIZEp=0 - J2 Mismatch Alarm (A1J2TIMp) when J21COMp and J21AISEp are 1, and J21SIZEp=0 - TC Unequipped Alarm (A1TCUQp) when TC1ENp and TC1AENp are 1 - TC Loss Of Lock Alarm (A1TCLLp) when TC1ENp and TC1AENp are 1 - TC Mismatch Alarm (A1TCTMp) when TC1ENp and TC1AENp are 1 - TC Loss Of Multiframe Alarm (A1TCLMp) when TC1ENp and TC1AENp are 1 - TC AIS Detected (A1TCAISp) when TC1ENp and TC1AENp are 1. - or when R1SELp is a 1 and any of: - Loss of pointer detected (B1LOPp) - VT AIS detected (B1AISp) - B Drop Bus Loss Of Clock (BDLOCp) - B Drop Bus Upstream AIS detected (BsUAISIp) and HEAISEp is 1. - or when R1SELp is 1 and RAISEp is 1 (drop VT from B side) and any of: - B Drop H4 Error (BsDH4Ep) when DV1SELp is 0 - Unequipped signal label (B1UNEQp) and UQAEp is 1 - Mismatch signal label (B1SLERp) - J2 Loss Of Lock Alarm (B1J2LOLp) when J21COMp and J21AISEp are 1, and J21SIZEp=0. - J2 Mismatch Alarm (B1J2TIMp) when J21COMp and J21AISEp are 1, and J21SIZEp=0 - TC Unequipped Alarm (B1TCUQp) when TC1ENp and TC1AENp are 1 - TC Loss Of Lock Alarm (B1TCLLp) when TC1ENp and TC1AENp are 1 - TC Mismatch Alarm (B1TCTMp) when TC1ENp and TC1AENp are 1 - TC Loss Of Multiframe Alarm (B1TCLMp) when TC1ENp and TC1AENp are 1 - TC AIS Detected (B1TCAISp) when TC1ENp and TC1AENp are 1. - or when Receive FIFO Error (R1FFEp) and RAISEp are 1. - or when a 1 is written to send receive AIS (R1AISp). - or when RTUN1p is invalid.
The AIS will be sent for one multiframe when a receive FIFO error occurs. The s in AsUAISIp, BsUAISIp, AsDH4Ep and BsDH4Ep represents the STS-1 or TUG in which the TU/VT has been selected, where s = 1-3 or A-C.
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DATA SHEET
Address 011 (cont.) Bit 0 Symbol RCLKIp Description
E1Mx16 TXC-04216
Receive E1 Line Clock Inversion: A common control for the four ports. A 0 enables the E1 receive data signal to be clocked out on positive (rising) RCOpn clock edges. A 1 causes E1 data to be clocked out on negative (falling) RCOpn clock edges. Add Indicator Inversion: A 1 causes the A and B Add bus output indicator signals (AADDp and BADDp) to be active high instead of active low when a time slot is added to the bus. A/B Add Bus Even Parity Generated: A 1 enables even parity to be generated, while a 0 enables odd parity to be generated. Parity is calculated over the data byte only. Interrupt/Event Positive/Negative Alarm Transition Selection: An event register bit will latch, and a software interrupt indication will occur, according to the transitions of any alarm given in the table below. The corresponding interrupt mask bit must be set if an interrupt is required. A hardware interrupt occurs when the hardware interrupt bit is also enabled (control bit HDWIEp is 1). These bits are disabled when a 0 is written to control bit LATENp. IPOSp 0 1 0 1 INEGp 0 0 1 1 Event Latches and Interrupt Occurs: not on any alarm transition on positive alarm transition (0 to 1) on negative alarm transition (1 to 0) on both positive and negative alarm transitions
012
7
ADDIp
6
APEp
5 4
IPOSp INEGp
3
RFIEp
RFI Enable: A common control bit for all four ports. A 1 enables an RFI indication to cause an interrupt. A 0 disables an RFI indication (bit 4 in V5 of the TU/VT) from causing an interrupt. Threshold Modulation Disabled: A 1 disables the threshold modulation capability in each of the four modulation circuits. A 0 enables threshold modulation capability in each of the four modulation circuits. A/B Drop Bus Even Parity Detected: This bit works in conjunction with the PDDOp control bit to determine the parity calculation in the drop direction. DPEp 0 0 1 1 PDDOp 0 1 0 1 Action (for both A and B buses) Odd parity check over drop data, SPE, and C1J1V1. Odd parity check over drop data only. Even parity check over drop data, SPE, and C1J1V1. Even parity check over drop data only.
2
THRSBYp
1
DPEp
Other than reporting the event, no action is taken upon parity error indication. 0 PDDOp A/B Drop Bus Parity Detected on Data Only: Common control bit for both buses. A 1 causes parity to be calculated over the data byte only. A 0 causes parity to be calculated over the data byte, SPE and C1J1V1 signals. Please refer to the table provided for DPEp.
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DATA SHEET
Address 013 Bit 7 Symbol HEAISEp Description
E1Mx16 TXC-04216
A/B H1/H2 or E1 Byte AIS Enable: Common control for both the A and B Drop buses. A 1 enables an AIS detected in either the SDH/SONET H1/H2 bytes, or in the E1 bytes, to generate a receive E1 line AIS and transmit an RDI (when enabled). Drop Bus V1 Select: Common control bit for both buses. A 0 selects the H4 byte to be used as the multiframe indicator. The V1 pulse, if present in the drop bus C1J1V1 signal, is ignored. A 1 selects the V1 pulses present in the A and B Drop bus C1J1V1 signals to be used for multiframe alignment. The H4 multiframe detector is disabled. Please refer to the table provided for control bit DV1REFp. Drop Bus V1 Reference Enable: Common control bit for both buses. Enabled when add bus timing is selected. In drop bus timing mode this bit must be set to zero. In add bus timing mode this control bit works in conjunction with the DV1SELp control bit according to the following table: DV1SELp 0 DV1REFp 0 Action Drop side uses H4 multiframe detector to determine V1 pulse Add side uses V1 pulse from add bus C1J1V1 signal Drop side uses H4 multiframe detector to determine V1 pulse Add side uses V1 pulse from drop side H4 multiframe detector Drop side uses V1 pulse from drop bus C1J1V1 signal Add side uses V1 pulse from add side C1J1V1 signal Drop side uses V1 pulse from drop side C1J1V1 signal Add side uses V1 pulse from drop side C1J1V1 signal
6
DV1SELp
5
DV1REFp
0
1
1
0
1
1
4
RDIENp
Transmit Remote Defect Indication Enable: Common control for both buses. This control bit enables incoming receive side (Drop) alarms to generate a Remote Defect Indication in the transmit (Add) direction. This bit also works in conjunction with the control bit 1BnRDIp found in the Operations (Control) Registers (048H, 078H, 0A8H, 0D8H). More details of how these control bits function can be found in the Operation Section on Remote Defect Indications. Force the NPI Column Unused Bytes to Zero: A 1 forces to 00H the unused bytes in the column following the NPI bytes when the NPI feature is enabled for the same TUG-3 (NPIAp, NPIBp or NPICp is a 1). A 0 forces the unused bytes following the NPI to a high impedance state on the A/B buses. Delay Drop Bus Indication Signal: A 1 increases the delay of the drop bus indication signals (ADINDp and BDINDp) by one clock cycle.
3
NULLZp
2
DDINDp
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 013 (cont.) Bit 1 Symbol UQAEp Description
E1Mx16 TXC-04216
Unequipped Alarm AIS/RDI/TC Alarm Enable: A common control for both the A and B Drop buses. A 1 enables a receive E1 line AIS, an RDI and both of the TC alarms (TCnODIp, TCnRDIp) to be transmitted when an unequipped alarm is detected in either the A or B Drop bus signals. Transmit O-Bit Channel With Zeros: A common control for all four ports. A 0 enables the microprocessor-written values for the O-bit channel and the unused bits in the K4 (Z7) byte to be transmitted. A 1 forces the O-bit channel and the unused bits in the K4 (Z7) byte to be transmitted as zero for all four ports.
0
TOBWZp
COMMON REGISTERS - PROVISIONING DESCRIPTIONS (p=1-4) Address 014 Bit 7-5 4 Symbol Unused(p) UEAMEp Description Unused: These bits must be written to 0. Unequipped Active Multiplex Line Enable: A 0 enables an unequipped channel or an unequipped supervisory channel to be generated in the Multiplexer Mode only, according to the table given below: Drop A Add B Action Unequipped or unequipped supervisory channel can be transmitted for the TU/VT selected on the A Bus. Unequipped or unequipped supervisory channel can be transmitted for the TU/VT selected on the B Bus.
B
A
A 1 enables an unequipped channel or unequipped supervisory channel to be transmitted on the active bus for the TU/VT selected. All other modes (Unidirectional Ring Mode and Bidirectional Ring Mode) always transmit an unequipped channel or an unequipped supervisory channel on the active bus only. See control bits UCHnEp and USCHnEp below (Addresses 04A, 07A, 0AA, 0DA) for associated control functions. 3 SE1AISp Select E1AIS: A 1 disables the TOH H1/H2n AIS detection circuit and enables the AIS detection circuit for the TOH E1n bytes. A 0 enables the AIS detection circuit for the H1/H2n bytes and disables that for the E1n bytes. Here the value of n is 1 for an STM-1 format and 1, 2 or 3 for an AU-3/STS-1 signal. V5 Alarm Detection Select 10: A 1 selects 10 consecutive RDI assertions for detection and recovery. A 0 selects 5 consecutive RDI assertions for detection and recovery. Pointer Tracking AIS to LOP Transition Enabled: A 1 enables the AIS to LOP transition in the pointer tracking state machine, as required by ETSI standards. A 0 will disable the transition, as required by Bellcore and ANSI standards. Hardware Interrupt Enable: A 1 enables the interrupt lead to be activated when an interrupt occurs. - 106 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
2
V5AL10p
1
PTALTEp
0
HDWIEp
DATA SHEET
Address 015 Bit 7 Symbol RESETp Description
E1Mx16 TXC-04216
Reset: A 1 clears to zero all controls, alarms, internal counters and performance counters, sets control bits AAHZEp and BAHZEp to 1, and reinitializes the receive and transmit FIFOs. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 1. Reset A Side Bus Alarms: A 1 clears the alarms associated with the A side bus and the LEXTCp alarm. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 2. Reset B Side Bus Alarms: A 1 clears the alarms associated with the B side bus and SPOT alarms. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 2. Reset Internal Processor (SPOT): A 1 resets the SPOT processor, without affecting its RAM. This bit will reset itself to 0 after the reset cycle is completed. See Note 1. Unused: These bits must be written to 0. Initialize Internal Processor (SPOT) Data RAM: A 1 initializes the Data RAM associated with the SPOT processor and resets the general purpose registers of this processor. This bit should only be set to 1 after a hardware reset (lead B4) or a software reset (control bit RESETp above) has been activated. This bit is self-clearing and will reset to 0 after the Data RAM initialization is complete. See Note 1. Unused: These bits must be written to 0. V4 Enable: A 1 enables the V4 access function in both receive and transmit directions. Unused: These bits must be written to 0. Transmit BIP-2 Disable (Test Bit): A 0 is used for normal operation and will allow the calculated N2 (Z6) BIP-2 and V5 BIP-2 values to be transmitted. A 1 will disable N2 (Z6) BIP-2 calculation as well as V5 BIP-2 calculation for all 4 ports and output zeros in its place. Unused: These bits must be written to 0.
6
RESTABp
5
RESTBBp
4
RESTSPp
3-1 0
Unused(p) INITSPp
0F1
7-4 3 2-0
Unused(p) V4ENp Unused(p) TxB2DISp
0F5
7
6-0
Unused(p)
Note 1: The control bits RESETp, RESTSPp and INITSPp in address 015H should not be applied simultaneously, but only serially (e.g., 80H followed by 01H, rather than 81H). Note 2: Control bits RESTABp and RESTBBp may be applied at the same time (60H).
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DATA SHEET
COMMON REGISTERS - INTERRUPT INDICATION REGISTER DESCRIPTIONS (p=1-4) Address 020 Bit 7 Symbol INTp Description
E1Mx16 TXC-04216
Software Interrupt Indication: A 1 indicates that one or more latched alarm(s) has occurred for which the corresponding interrupt mask bit(s) is/are set to 1. External Clock Interrupt Indication: Enabled when a 1 is written into the ECKMSKp bit. A 1 indicates that the external clock at input lead EXTCK has failed (i.e., LEXTCp=1). A Side Interrupt Indication: Enabled when a 1 is written into the ASMSKp bit. A 1 indicates that an alarm has occurred in one of the A-side alarm registers (i.e., 022H and 024H, bits 2, 1 and 0). B Side Interrupt Indication: Enabled when a 1 is written into the BSMSKp bit. A 1 indicates that an alarm has occurred in one of the B-side alarm registers (i.e., 026H and 028H, bits 2, 1 and 0). Port 4 Interrupt Indication: Enabled when a 1 is written into the P4MSKp bit. A 1 indicates that an alarm has occurred in one of the port 4 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 3 Interrupt Indication: Enabled when a 1 is written into the P3MSKp bit. A 1 indicates that an alarm has occurred in one of the port 3 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 2 Interrupt Indication: Enabled when a 1 is written into the P2MSKp bit. A 1 indicates that an alarm has occurred in one of the port 2 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 1 Interrupt Indication: Enabled when a 1 is written into the P1MSKp bit. A 1 indicates that an alarm has occurred in one of the port 1 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H).
6
EXTCKp
5
ASIDEp
4
BSIDEp
3
PORT4p
2
PORT3p
1
PORT2p
0
PORT1p
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DATA SHEET
COMMON REGISTERS - INTERRUPT MASK DESCRIPTIONS (p=1-4) Address 016 Bit 7-1 0 Symbol Unused(p) SPTMSKp Description Unused: These bits must be written to 0.
E1Mx16 TXC-04216
SPOT Status Interrupt Mask: A 1 enables a hardware interrupt (lead INTp/IRQp) and a software interrupt indication (INTp) when a SPOT alarm has occurred in any of the SPOT alarm register bits (address 028H, bits 7, 6 and 4). A 0 disables the SPOT alarms from causing an interrupt. See Note 1. Receive A Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred in an A-side port n alarm register while PnMSKp is set for port n. A 0 disables the A side receive alarms for port n from causing an interrupt. See Note 1. Receive B Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred in a B-side port n alarm register while PnMSKp is set for port n. A 0 disables the B side receive alarms for port n from causing an interrupt. See Note 1. Transmit FIFO Error A Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred for an A-side port n transmit FIFO while PnMSKp is set for port n. A 0 disables a transmit FIFO error A side alarm for port n from causing an interrupt. See Note 1. Transmit FIFO Error B Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred for a B-side port n transmit FIFO while PnMSKp is set for port n. A 0 disables a transmit FIFO error B side alarm for port n from causing an interrupt. See Note 1. Transmit Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred for one of the port n transmit alarms while PnMSKp is set for port n. A 0 disables a transmit alarm from causing an interrupt. See Note 1. Receive FIFO Error Status Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indication (INTp) when an alarm has occurred for a port n receive FIFO while PnMSKp is set for port n. A 0 disables a receive FIFO error alarm for port n from causing an interrupt. See Note 1.
017
7, 5, 3, 1
RPTnAp (n=4-1)
6, 4, 2, 0
RPTnBp (n=4-1)
018
7, 5, 3, 1
TFIFOnAp (n=4-1)
6, 4, 2, 0
TFIFOnBp (n=4-1)
019
7, 6, 5, 4
TPORTnp (n=4-1)
3, 2, 1, 0
RFIFOnp (n=4-1)
Note 1:
Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register locations to which these interrupt masks apply. RPTnAp or RPTnBp are not required to be set to 1 to enable an interrupt for AnRFIp or BnRFIp alarms. Control bit HDWIEp must be set to 1 if a hardware interrupt is required.
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DATA SHEET
Address 021 Bit 7 6 Symbol Unused(p) ECKMSKp Description Unused: This bit must be written to 0.
E1Mx16 TXC-04216
External Clock Interrupt Mask Bit: A 1 enables a hardware interrupt (lead INTp/IRQp) and software interrupt indications (INTp and EXTCKp) when an external clock failure alarm has occurred. See Note 1. A Side Interrupt Mask Bit: A 1 enables the A Side Interrupt Indication (ASIDEp). See Note 1. B Side Interrupt Mask Bit: A 1 enables the B Side Interrupt Indication (BSIDEp). See Note 1. Port 4 Interrupt Mask Bit: A 1 enables the Port 4 Interrupt Indication (PORT4p). It permits a hardware interrupt (lead INTp/IRQp) and a software interrupt indication (INTp) when an alarm has occurred in one of the alarm registers for port 4, when the corresponding RPT4A, RPT4B, TFIFO4A, TFIFO4B, RFIFO4 or TPORT4 mask bit is set to 1. See Note 1. Port 3 Interrupt Mask Bit: A 1 enables the Port 3 Interrupt Indication (PORT3p). It permits a hardware interrupt (lead INTp/IRQp) and a software interrupt indication (INTp) when an alarm has occurred in one of the alarm registers for port 3, when the corresponding RPT3A, RPT3B, TFIFO3A, TFIFO3B, RFIFO3 or TPORT3 mask bit is set to 1. See Note 1. Port 2 Interrupt Mask Bit: A 1 enables the Port 2 Interrupt Indication (PORT2p). It permits a hardware interrupt (lead INTp/IRQp) and a software interrupt indication (INTp) when an alarm has occurred in one of the alarm registers for port 2, when the corresponding RPT2A, RPT2B, TFIFO2A, TFIFO2B, RFIFO2 or TPORT2 mask bit is set to 1. See Note 1. Port 1 Interrupt Mask Bit: A 1 enables the Port 1 Interrupt Indication (PORT1p). It permits a hardware interrupt (lead INTp/IRQp) and a software interrupt indication (INTp) when an alarm has occurred in one of the alarm registers for port 1, when the corresponding RPT1A, RPT1B, TFIFO1A, TFIFO1B, RFIFO1 or TPORT1 mask bit is set to 1. See Note 1.
5 4 3
ASMSKp BSMSKp P4MSKp
2
P3MSKp
1
P2MSKp
0
P1MSKp
Note 1:
Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register locations to which these interrupt masks apply. RPTnAp or RPTnBp is not required to be set to 1 to enable an interrupt for AnRFIp or BnRFIp alarms. Control bit HDWIEp must be set to 1 if a hardware interrupt is required.
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DATA SHEET
A/B DROP AND ADD BUS - STATUS REGISTER DESCRIPTIONS (p=1-4) Address 022 023 Bit 7-0 7 ADLOCp Symbol Description
E1Mx16 TXC-04216
Same bit definitions as in register 023H, except the bits are latched. A Drop Bus Loss Of Clock: A 1 indicates that the A Drop bus has detected a loss of clock. An alarm occurs when the input drop clock is stuck high or low for 1000 ns 500 ns. Recovery to 0 occurs on the first clock transition. Please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. A Add Bus Loss Of Clock: A 1 indicates that the A Add bus has detected a loss of clock, when add bus timing is selected. A loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. An alarm occurs when the input add clock is stuck high or low for 1000 ns 500 ns. Recovery to 0 occurs on the first clock transition. A Drop Bus Parity Error Detected: A 1 indicates that an even or odd parity error has been detected in the A Drop bus signals. Other than an alarm indication, no action is taken. Parity is monitored for each drop bus clock cycle. Unused: These bits read out as 0. A Side Received Upstream AIS Indication - AU-3 C/STS-1 No. 3: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 C/STS-1 No. 3. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E13 byte for AU-3 C/ STS-1 No. 3. Disabled when the format is an AU-4 VC-4, or STS-1. A Side Received Upstream AIS Indication - AU-3 B/STS-1 No. 2: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 B/STS-1 No. 2. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E12 byte for AU-3 B/ STS-1 No. 2. Disabled when the format is an AU-4 VC-4, or STS-1. A Side Received Upstream AIS Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 A/STS-1 No. 1, or in the AU-4 VC-4 signal. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 025H, except the bits are latched.
6
AALOCp
5
ADPARp
4-3 2
Unused(p) A3UAISIp
1
A2UAISIp
0
A1UAISIp
024
7-0
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DATA SHEET
Address 025 Bit 7 Symbol LEXTCp Description
E1Mx16 TXC-04216
Loss Of External Clock: A 1 indicates an external loss of clock alarm when the external clock input EXTCK (lead C13) is stuck high or low for 1000 ns 500 ns. Recovery to 0 occurs on the first clock transition. Unused: These bits read out as 0. A Drop Bus Loss of H4 Indication - AU-3 C/STS-1 No. 3: Loss of multiframe for AU-3 C/STS-1 No. 3 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. A Drop Bus Loss of H4 Indication - AU-3 B/STS-1 No. 2: Loss of multiframe for AU-3 B/STS-1 No. 2 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. A Drop Bus Loss of H4 Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: Loss of multiframe for AU-3 A/STS-1 No. 1, AU-4 VC-4 or STS-1 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This bit is forced to 1 at power-up. Same bit definitions as in register 027H, except the bits are latched.
6-3 2
Unused(p) A3DH4Ep
1
A2DH4Ep
0
A1DH4Ep
026
7-0
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DATA SHEET
Address 027 Bit 7 Symbol BDLOCp Description
E1Mx16 TXC-04216
B Drop Bus Loss Of Clock: A 1 indicates that the B Drop bus has detected a loss of clock. An alarm occurs when the input drop clock is stuck high or low for 1000 ns 500 ns. Recovery to 0 occurs on the first clock transition. Please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. B Add Bus Loss Of Clock: A 1 indicates that the B Add bus has detected a loss of clock, when add bus timing is selected. A loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. An alarm occurs when the input drop clock is stuck high or low for 1000 ns 500 ns. Recovery to 0 occurs on the first clock transition. B Drop Bus Parity Error Detected: A 1 indicates that an even or odd parity error has been detected in the B Drop bus signals. Other than an alarm indication, no action is taken. Parity is monitored for each drop bus clock cycle. Unused: These bits read out as 0. B Side Received Upstream AIS Indication - AU-3 C/STS-1 No. 3: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 C/STS-1 No. 3. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E13 byte for AU-3 C/ STS-1 No. 3. Disabled when the format is a AU-4 VC-4, or STS-1. B Side Received Upstream AIS Indication - AU-3 B/STS-1 No. 2: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 B/STS-1 No. 2. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E12 byte for AU-3 B/ STS-1 No. 2. Disabled when the format is a AU-4 VC-4, or STS-1 B Side Received Upstream AIS Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: When control bit SE1AISp is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 A/STS-1 No. 1, or in the AU-4 VC-4 signal. When control bit SE1AISp is 1, a 1 indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 029H, except the bits are latched.
6
BALOCp
5
BDPARp
4-3 2
Unused(p) B3UAISIp
1
B2UAISIp
0
B1UAISIp
028
7-0
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DATA SHEET
Address 029 Bit 7 Symbol SPTLOCp Description
E1Mx16 TXC-04216
Internal Processor (SPOT) Loss of Clock: The 29.16 MHz clock internally derived from the 58.32 MHz desynchronizer clock input (EXTCK) is monitored for loss of clock. Loss of clock is declared and this bit is set to 1 if this clock is stuck high or low for 1000 500 ns. Recovery to 0 occurs on the first clock transition. Watch Dog Timer Expired: This bit is set to 1 when the SPOT is unable to service all requests in a timely manner. Unused: This bits reads out as 0. Parity Error: This bit is set to 1 when a parity error is detected while reading the Instruction RAM of the SPOT. Unused: This bits reads out as 0. B Drop Bus Loss of H4 Indication - AU-3 C/STS-1 No. 3: Loss of multiframe for AU-3 C/STS-1 No. 3 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. B Drop Bus Loss of H4 Indication - AU-3 B/STS-1 No. 2: Loss of multiframe for AU-3 B/STS-1 No. 2 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. B Drop Bus Loss of H4 Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: Loss of multiframe for AU-3 A/STS-1 No. 1, AU-4 VC-4 or STS-1 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SELp is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This bit is forced to 1 at power-up.
6 5 4 3 2
WDTEXPp Unused(p) PERRp Unused(p) B3DH4Ep
1
B2DH4Ep
0
B1DH4Ep
PORT n - DESYNCHRONIZER CONTROL REGISTER DESCRIPTIONS (p=1-4) Address 049 Port 1 079 Port 2 0A9 Port 3 0D9 Port 4 Bit 7-0 Symbol Pointer Leak Rate Value(p) Description Desynchronizer Pointer Leak Rate Register - Port n: The count written into this location is used for the internal leak rate buffer, and represents the average leak rate. A count of one represents 8 frames, or 2 multiframes, in the rate of occurrence of pointer movements from the number of counts read from the positive and negative stuff counters.
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DATA SHEET
PORT n - PROVISIONING REGISTER DESCRIPTIONS (p=1-4) Address 04A Port 1 07A Port 2 0AA Port 3 0DA Port 4 Bit 7 6 5 Symbol TnSEL1p TnSEL0p RnSELp Description
E1Mx16 TXC-04216
Transmit Port n A/B Drop/Add Bus Selection: The table below lists the selection criteria for the eight available modes of operation of port n: TnSEL1p TnSEL0p RnSELp Operating Mode 0 0 0 A Drop only (Drop) 0 0 1 B Drop only (Drop) 0 1 0 A Drop A Add (Single Unidirectional Ring) 0 1 1 B Drop B Add (Single Unidirectional Ring) 1 0 0 A Drop B Add (Multiplexer) 1 0 1 B Drop A Add (Multiplexer) 1 1 0 A Drop A and B Add (Dual Unidirectional Ring) 1 1 1 B Drop B and A Add (Dual Unidirectional Ring)
4
UCHnEp
Unequipped Channel for Port n Enabled: The UCHnEp control bit works in conjunction with the USCHnEp control bit (in bit position 3) according to the following table: UCHnEp 0 1 USCHnEp Action X Normal Operation. 0 Unequipped TU/VT generated. An unequipped TU/VT consists of a normal NDF, size bits equal to 10, a fixed pointer equal to 105, and all other bytes equal to 00H. 1 Unequipped supervisory TU/VT generated. An unequipped supervisory TU/VT consists of a normal NDF, size bits equal to 10, a fixed pointer equal to 105, and a valid J2 byte. The V5 byte will consist of a valid BIP-2, with the signal label sent as zeros by setting control bit TnTx Label to 0. The N2 (Z6) byte can be sent as zero by setting TCnENp=0 and TxB2DISp=1. The K4 (Z7) byte, bits 1, 2, 3, 4 and 8 can be sent as zeros by setting control bit TOBWZp=1. The RDI bits, V5 bit 8 and K4 (Z7) bits 5, 6 and 7 can be disabled and sent as zeros by setting control bit RDIENp=0.
1
Note: X = don't care (0 or 1). See UEAMEp description in register 014H and the Operation section under E1Mx16 Unequipped Operation for further description. 3 2 USCHnEp BYPASnp Unequipped Supervisory Channel for Port n Enabled: Works in conjunction with the UCHnEp bit according to the table given above. Bypass Codec of Port n: A 1 disables the HDB3 Codec (coder and decoder) of port n for NRZ operation. A 0 enables the HDB3 Codec for rail operation.
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DATA SHEET
Address 04A Port 1 07A Port 2 0AA Port 3 0DA Port 4 (cont.) 04B Port 1 07B Port 2 0AB Port 3 0DB Port 4 Bit 1 Symbol RnENp Description
E1Mx16 TXC-04216
Receive Port n Enable: A 1 enables the receive data (NRZ or rail) output and clock output for port n when lead QUIETpn is low. A 0 forces the data and clock output leads to a high impedance state. The four bits power up as 0 and are reset to 0. A 1 must be written to these control bits to enable the port E1 outputs. Unused: This bit must be written to 0. A Side Drop Bus Port n TU/VT Selection Output Enable: A 1 enables the drop bus ADINDp signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. B Side Drop Bus Port n TU/VT Selection Output Enable: A 1 enables the drop bus BDINDp signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. A Side Add Bus Port n TU/VT Selection Output Enable: A 1 enables the add bus AAINDp signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. B Side Add Bus Port n TU/VT Selection Output Enable: A 1 enables the add bus BAINDp signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. PRBS Analyzer Sampling Tx E1 Signal for Port n: A 1 enables the internal PRBS analyzer to sample the Tx E1 signal to be sent to the synchronizer. A 0 enables the internal PRBS analyzer to sample the E1 signal to be sent to the Rx E1 ports. PRBS Analyzer Enable for Port n: A1 enables the internal 215-1 PRBS analyzer. A 0 disables the analyzer. PRBS Generator Enable for Port n: A 1 enables the internal 215-1 PRBS generator. A 0 disables the generator. FEBE and RDI Disabled For Port n: Enabled when the single unidirectional mode (control bits TnSEL1p, TnSEL0p are equal to 01) is selected. A 1 disables receive side alarms or an out of range condition from generating an RDI. In addition, the REI (FEBE) value is transmitted as a zero. Unused: This bit must be written to 0. Receive TU/VT Selection for Port n: The seven-bit binary code written into this location selects the TU/VT that is to be dropped from the A and/or B-side drop bus. Control bits TnSEL1p, TnSEL0p and RnSELp determine the drop bus(es) that the data is dropped from. If no TU/VT is selected, the microprocessor should either write a 1 to control bit RnAISp, thereby forcing an E1 AIS, or should write a 0 to RnENp, which will tristate the port n data and clock output leads. Also, the FEBE and RDI values are transmitted as zero. Transmit TU/VT Selection for Port n: The seven-bit binary code written into this location selects the TU/VT that is to be added to the A and/or B-side add bus. Control bits TnSEL1p, TnSEL0p and RnSELp determine the add bus(es) that the data is added to. If no TU/VT is selected, the A or B add bus will tristate.
0 7
Unused(p) ADnENp
6
BDnENp
5
AAnENp
4
BAnENp
3
ANAnTxp
2 1 0
ANAnENp
PRBSnENp
FRDISnp
04C Port 1 07C Port 2 0AC Port 3 0DC Port 4
7 6-0
Unused(p) RTUNnp
04D Port 1 07D Port 2 0AD Port 3 0DD Port 4
7 6-0
Unused(np) Unused: This bit must be written to 0. TTUNnp
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PORT n - RECEIVE STATUS REGISTER AND COUNTER DESCRIPTIONS (A SIDE) (p=1-4)
E1Mx16 TXC-04216
The following descriptions pertain to the status registers and counters assigned to Port n. The status registers provide two readable bit positions per alarm. One bit (in an odd-numbered address) indicates the detected alarm as unlatched. The second bit (in the preceding even-numbered address) provides the alarm status as an latched alarm indication. A latched bit position is set on positive, negative, or both positive and negative transitions of the alarm, or on a positive level of the alarm. A latched alarm is cleared on a microprocessor read cycle of its address. During a read cycle for a counter, internal logic holds any increment to the counter until the read cycle is complete, and then updates the counter afterwards. Address 030 Port 1 060 Port 2 090 Port 3 0C0 Port 4 031 Port 1 061 Port 2 091 Port 3 0C1 Port 4 Bit 7-0 Symbol Latched An Alarms(np) AnAISp AnLOPp Description Same alarms as the unlatched indications in the following address locations (7-0), except that these alarm states are latched.
7 6
A Drop Bus Port n TU/VT AIS Alarm: A 1 indicates that an AIS has been detected in the V1/V2 pointer bytes for the TU/VT selected. A Drop Bus Port n Loss Of TU/VT Pointer Alarm: A 1 indicates that a loss of pointer has been detected in the V1/V2 pointer bytes for the TU/ VT selected. A Drop Bus Port n TU/VT Pointer Size Error Indication: A 1 indicates that the receive size indicator in the pointer (Bits 5 and 6 in the V1 pointer byte) is not 10 for the TU/VT selected. The detection and recovery time is immediate. A Drop Bus Port n New Data Flag Indication: A 1 indicates that a New Data Flag (1001 or 0001/1101/1011/1000) has been detected in the V1 pointer byte for the TU/VT selected (i.e., bits 1-4 in the V1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). A Drop Bus Port n Remote Server Defect Indication: A 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 101), or an RDI has been detected coming from older equipment (bit 8 in V5 byte equals 1 when bits 6 and 7 in K4 (Z7) byte are equal to 00 or 11). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. A Drop Bus Port n Remote Failure Indication: A 1 indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate. A Drop Bus Port n Unequipped Indication: A 1 indicates that an Unequipped status has been detected in the V5 signal label (Bits 5-7 in V5 byte = 0) for the TU/VT selected in the A side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five or more consecutive signal labels are received not equal to 000.
5
AnSIZEp
4
AnNDFp
3
AnRDISp
2
AnRFIp
1
AnUNEQp
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Address 031 Port 1 061 Port 2 091 Port 3 0C1 Port 4 (cont.) Bit 0 Symbol AnSLERp Description
E1Mx16 TXC-04216
A Drop Bus Port n Signal Label Mismatch Indication: A 1 indicates that the receive signal label (Bits 5-7 in V5 byte) does not match the microprocessor-written signal label in the TU/VT selected for the A side drop bus. Five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. Recovery occurs upon receipt of five or more consecutive correct signal labels, or 001 values. A Drop Bus Port n Positive Pointer Justification Counter: A four-bit counter that increments on a positive pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Negative Pointer Justification Counter: A four-bit counter that increments on a negative pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected for the TU/VT selected. A maximum of two errors can occur each frame. These two errors cause a single count if the BLOCKp control bit is set to 1. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n FEBE Counter: An 8-bit counter which counts the number of FEBE errors received (Bit 3 in V5 byte = 1) for the TU/VT selected. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Received Signal Label: These three bit positions correspond to the three signal label bits in bits 5 through 7 of the V5 byte in the TU/VT selected. This location is updated every 500 microseconds. Bit 2 corresponds to bit 7 in the V5 byte. These bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. Code 1 (001) has been implemented in hardware and does not have to be written into this location. Same alarms as the corresponding address 04F, 07F, 0AF, 0DF bit positions, except that these alarms are latched.
032 Port 1 062 Port 2 092 Port 3 0C2 Port 4
7-4
AnPJ Counter(p)
3-0
AnNJ Counter(p)
033 Port 1 063 Port 2 093 Port 3 0C3 Port 4 034 Port 1 064 Port 2 094 Port 3 0C4 Port 4 035 Port 1 065 Port 2 095 Port 3 0C5 Port 4
7-0
AnBIP2 Counter(p)
7-0
AnFEBE Counter(p)
7-3 2-0
Unused(np) Unused: These bits read out as indeterminate. An Rx Label(p)
04E Port 1 07E Port 2 0AE Port 3 0DE Port 4
7-6
Latched An Alarms(p) Latched An Alarms(p)
5-4 3-2
Unused(np) Unused: These bits read out as zero. Same alarms as the corresponding address 04F, 07F, 0AF, 0DF bit positions, except that these alarms are latched.
1-0
Unused(np) Unused: These bits read out as zero.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 04F Port 1 07F Port 2 0AF Port 3 0DF Port 4 Bit 7 Symbol AnRDIPp Description
E1Mx16 TXC-04216
A Drop Bus Port n Remote Payload Defect Indication: A 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 010). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. A Drop Bus Port n Remote Connectivity Defect Indication: A 1 indicates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 110). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. A Drop Bus Port n J2 Loss Of Lock Alarm: Enabled when control bit J2nSIZEp is a 0, and control bit J2nCOMp is a 1. A 1 indication occurs when the alignment of the 16-byte J2 trace identifier label (message) has not been established. A Drop Bus Port n J2 Trail Trace Mismatch Alarm: Enabled when control bit J2nSIZEp is a 0, and control bit J2nCOMp is a 1. A 1 indicates that the stable 16-byte message did not match for one message time. Recovery occurs when the J2 state machine loses lock and then acquires lock with a 16-byte stable J2 message that matches the J2 comparison message written by the microprocessor. A Drop Bus Port n Receive K4 (Z7) Byte: The eight bits in this register position correspond to the K4 (Z7) byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the K4 (Z7) byte. A Drop Bus Port n Receive O-bits: The two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communication bits received in the TU/VT selected. Bit 7 corresponds to bit 3 in the second justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. The two nibbles written into this register location will be from the same frame. Same alarms as the following address locations (7-1), except that these alarm states are latched.
6
AnRDICp
5-4 3
Unused(np) Unused: These bits read out as zero. AnJ2LOLp
2
AnJ2TIMp
1-0 038 Port 1 068 Port 2 098 Port 3 0C8 Port 4 039 Port 1 069 Port 2 099 Port 3 0C9 Port 4 7-0
Unused(np) Unused: These bits read out as zero. An Receive K4 (Z7) Byte(p) An Receive O-Bits(p)
7-0
05A Port 1 08A Port 2 0BA Port 3 0EA Port 4
7-1
Latched An Alarms(p)
0
Unused(np) Unused: This bit reads out as indeterminate.
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DATA SHEET
Address 05B Port 1 08B Port 2 0BB Port 3 0EB Port 4 Bit 7 Symbol AnTCUQp Description
E1Mx16 TXC-04216
A Drop Bus Port n Tandem Connection Unequipped Alarm: A TC unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. A Drop Bus Port n Tandem Connection AIS Alarm: A TC AIS alarm indication (a 1) occurs when bit 4 in the N2 (Z6) byte is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. A Drop Bus Port n Tandem Connection Loss Of Multiframe Alarm: A TC loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the N2 (Z6) byte. Recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. A Drop Bus Port n Bus Tandem Connection Trail Trace Message Loss Of Lock Alarm: An alarm indication (a 1) occurs when the alignment of the 16-byte N2 (Z6) Tandem Connection Trace identifier label (message) has not been established. A Drop Bus Port n Bus Tandem Connection Trail Trace Message Mismatch Alarm: An alarm indication (a 1) indicates that the stable Tandem Connection 16-byte message did not match for one message time. Recovery to 0 occurs when the N2 (Z6) byte TC message state machine loses lock and then acquires lock with a 16-byte stable N2 (Z6) byte message that matches the N2 (Z6) byte comparison message written by the microprocessor. A Drop Bus Port n Tandem Connection ODI Alarm: A TC ODI alarm indication (a 1) occurs when N2 (Z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. A Drop Bus Port n Tandem Connection RDI Alarm: A TC RDI alarm indication (a 1) occurs when N2 (Z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. A Drop Bus Port n Tandem Connection BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. A maximum of two errors can be counted each frame. These two errors cause a single count if the BLOCKp control bit is set to 1. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Tandem Connection REI Counter: An 8-bit counter which counts the number of REI errors detected in bit 5 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read.
6
AnTCAISp
5
AnTCLMp
4
AnTCLLp
3
AnTCTMp
2
AnTCODIp
1
AnTCRDIp
0 100 Port 1 200 Port 2 300 Port 3 400 Port 4 7-0
Unused(np) Unused: This bit reads out as indeterminate. An TC BIP-2 Error Counter(p)
101 Port 1 201 Port 2 301 Port 3 401 Port 4
7-0
An TC REI Error Counter(p)
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 102 Port 1 202 Port 2 302 Port 3 402 Port 4 116 Port 1 216 Port 2 316 Port 3 416 Port 4 Bit 7-0 Symbol An TC OEI Error Counter(p) An Receive V4 Byte(p) Description
E1Mx16 TXC-04216
A Drop Bus Port n Tandem Connection OEI Counter: An 8-bit counter which counts the number of OEI errors detected in bit 6 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Receive V4 Byte: When control bit V4ENp is 1, the eight bits in this register position correspond to the V4 byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the V4 byte.
7-0
PORT n - RECEIVE STATUS REGISTER AND COUNTER DESCRIPTIONS (B SIDE) (p=1-4) Address 03A Port 1 06A Port 2 09A Port 3 0CA Port 4 03B Port 1 06B Port 2 09B Port 3 0CB Port 4 Bit 7-0 Symbol Description
Latched Bn Same alarms as the following address locations (7-0), except that these Alarms(p) alarm states are latched.
7 6
BnAISp BnLOPp
B Drop Bus Port n TU/VT AIS Alarm: A 1 indicates that an AIS has been detected in the V1/V2 pointer bytes for the TU/VT selected. B Drop Bus Port n Loss Of TU/VT Pointer Alarm: A 1 indicates that a loss of pointer has been detected in the V1/V2 pointer bytes for the TU/ VT selected. B Drop Bus Port n TU/VT Pointer Size Error Indication: A 1 indicates that the receive size indicator in the pointer (Bits 5 and 6 in the V1 pointer byte) is not 10 for the TU/VT selected. The detection and recovery time is immediate. B Drop Bus Port n New Data Flag Indication: A 1 indicates that a New Data Flag (1001 or 0001/1101/1011/1000) has been detected in the V1 pointer byte for the TU/VT selected (i.e., bits 1-4 in the V1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). B Drop Bus Port n Remote Server Defect Indication: A 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 101), or an RDI has been detected coming from older equipment (bit 8 in V5 byte equals 1 when bits 6 and 7 in K4 (Z7) byte are equal to 00 or 11). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. B Drop Bus Port n Remote Failure Indication: A 1 indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate.
5
BnSIZEp
4
BnNDFp
3
BnRDISp
2
BnRFIp
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DATA SHEET
Address 03B Port 1 06B Port 2 09B Port 3 0CB Port 4 (cont.) Bit 1 Symbol BnUNEQp Description
E1Mx16 TXC-04216
B Drop Bus Port n Unequipped Indication: A 1 indicates that an Unequipped status has been detected in the V5 signal label (Bits 5-7 in V5 byte = 0) for the TU/VT selected in the B side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five or more consecutive signal labels are received not equal to 000. B Drop Bus Port n Signal Label Mismatch Indication: A 1 indicates that the receive signal label (Bits 5-7 in V5 byte) does not match the microprocessor-written signal label in the TU/VT selected for the B side drop bus. Five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. Recovery occurs upon receipt of five or more consecutive correct signal labels, or 001 values. B Drop Bus Port n Positive Pointer Justification Counter: A four-bit counter that increments on a positive pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Negative Pointer Justification Counter: A four-bit counter that increments on a negative pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected for the TU/VT selected. A maximum of two errors can occur each frame. These two errors cause a single count if the BLOCKp control bit is set to 1. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n FEBE Counter: An 8-bit counter which counts the number of FEBE errors received (Bit 3 in V5 byte = 1) for the TU/VT selected. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Received Signal Label: These three bit positions correspond to the three signal label bits located in bits 5 through 7 of the V5 byte for the TU/VT selected. This location is updated every 500 microseconds. Bit 2 corresponds to bit 7 in the V5 byte. These bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. Code 1 (001) has been implemented in hardware and does not have to be written into this location.
0
BnSLERp
03C Port 1 06C Port 2 09C Port 3 0CC Port 4
7-4
BnPJ Counter(p)
3-0
BnNJ Counter(p)
03D Port 1 06D Port 2 09D Port 3 0CD Port 4 03E Port 1 06E Port 2 09E Port 3 0CE Port 4 03F Port 1 06F Port 2 09F Port 3 0CF Port 4
7-0
BnBIP2 Counter(p)
7-0
BnFEBE Counter(p)
7-3 2-0
Unused(np) Unused: These bits read out as indeterminate. Bn RX Label(p)
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 05E Port 1 08E Port 2 0BE Port 3 0EE Port 4 Bit 7-6 Symbol Latched Bn Alarms(p) Latched Bn Alarms(p) BnRDIPp Description
E1Mx16 TXC-04216
Same alarms as the corresponding address 05F, 08F, 0BF, 0EF bit positions except that these alarms are latched.
5-4 3-2
Unused(np) Unused: These bits read out as zero. Same alarms as the corresponding address 05F, 08F, 0BF, 0EF bit positions except that these alarms are latched.
1-0 05F Port 1 08F Port 2 0BF Port 3 0EF Port 4 7
Unused(np) Unused: These bits read out as zero. B Drop Bus Port n Remote Payload Defect Indication: A 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 010). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. B Drop Bus Port n Remote Connectivity Defect Indication: A 1 indicates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 110). The number of consecutive events used for detection and recovery is determined by control bit V5AL10p. B Drop Bus Port n J2 Loss Of Lock Alarm: Enabled when control bit J2nSIZEp is a 0, and control bit J2nCOMp is a 1. A 1 indication occurs when the alignment of the 16-byte J2 trace identifier label (message) has not been established. B Drop Bus Port n J2 Trail Trace Mismatch Alarm: Enabled when control bit J2nSIZEp is a 0, and control bit J2nCOMp is a 1. A 1 indicates that the stable 16-byte message did not match for one message time. Recovery occurs when the J2 state machine loses lock and then acquires lock with a 16-byte stable J2 message that matches the J2 comparison message written by the microprocessor.
6
BnRDICp
5-4 3
Unused(np) Unused: These bits read out as zero. BnJ2LOLp
2
BnJ2TIMp
1-0 042 Port 1 072 Port 2 0A2 Port 3 0D2 Port 4 043 Port 1 073 Port 2 0A3 Port 3 0D3 Port 4 7-0
Unused(np) Unused: These bits read out as zero. Bn Receive B Drop Bus Port n Receive K4 (Z7) Byte: The eight bits in this register position correspond to the K4 (Z7) byte received for the TU/VT selected. K4 (Z7) Bit 7 corresponds to bit 1 in the K4 (Z7) byte. Byte(p) Bn Receive B Drop Bus Port n Receive O-bits: The two nibbles (bits 7-4 and 3-0) O-Bits(p) in this register correspond to the two sets of four overhead communication bits received in the TU/VT selected. Bit 7 corresponds to bit 3 in the second justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. The two nibbles written into this register location will be from the same frame. Latched Bn Alarms(p) Same alarms as the following address locations (7-1), except that these alarm states are latched.
7-0
05C Port 1 08C Port 2 0BC Port 3 0EC Port 4
7-1
0
Unused(np) Unused: This bit reads out as indeterminate.
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DATA SHEET
Address 05D Port 1 08D Port 2 0BD Port 3 0ED Port 4 Bit 7 Symbol BnTCUQp Description
E1Mx16 TXC-04216
B Drop Bus Port n Tandem Connection Unequipped Alarm: A TC unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. B Drop Bus Port n Tandem Connection AIS Alarm: A TC AIS alarm indication (a 1) occurs when bit 4 in the N2 (Z6) byte is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. B Drop Bus Port n Tandem Connection Loss Of Multiframe Alarm: A TC loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the N2 (Z6) byte. Recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. B Drop Bus Port n Bus Tandem Connection Trail Trace Message Loss Of Lock Alarm: An alarm indication (a 1) occurs when the alignment of the 16-byte N2 (Z6) Tandem Connection Trace identifier label (message) has not been established. B Drop Bus Port n Bus Tandem Connection Trail Trace Message Mismatch Alarm: An alarm indication (a 1) indicates that the stable Tandem Connection 16-byte message did not match for one message time. Recovery to 0 occurs when the N2 (Z6) byte TC message state machine loses lock and then acquires lock with a 16-byte stable N2 (Z6) byte message that matches the N2 (Z6) byte comparison message written by the microprocessor. B Drop Bus Port n Tandem Connection ODI Alarm: A TC ODI alarm indication (a 1) occurs when N2 (Z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. B Drop Bus Port n Tandem Connection RDI Alarm: A TC RDI alarm indication (a 1) occurs when N2 (Z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. B Drop Bus Port n Tandem Connection BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. A maximum of two errors can be counted each frame.These two errors cause a single count if the BLOCKp control bit is set to 1. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Tandem Connection REI Counter: An 8-bit counter which counts the number of REI errors detected in bit 5 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read.
6
BnTCAISp
5
BnTCLMp
4
BnTCLLp
3
BnTCTMp
2
BnTCODIp
1
BnTCRDIp
0 180 Port 1 280 Port 2 380 Port 3 480 Port 4 7-0
Unused(np) Unused: This bit reads out as indeterminate. Bn TC BIP-2 Error Counter(p)
181 Port 1 281 Port 2 381 Port 3 481 Port 4
7-0
Bn TC REI Error Counter(p)
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 182 Port 1 282 Port 2 382 Port 3 482 Port 4 196 Port 1 296 Port 2 396 Port 3 496 Port 4 Bit 7-0 Symbol Bn TC OEI Error Counter(p) Bn Receive V4 Byte(p) Description
E1Mx16 TXC-04216
B Drop Bus Port n Tandem Connection OEI Counter: An 8-bit counter which counts the number of OEI errors detected in bit 6 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Receive V4 Byte: When control bit V4ENp is 1, the eight bits in this register position correspond to the V4 byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the V4 byte.
7-0
STATUS REGISTERS - PORT n (A and B SIDES) (p=1-4) Address 044 Port 1 074 Port 2 0A4 Port 3 0D4 Port 4 Bit 7 6 5-0 045 Port 1 075 Port 2 0A5 Port 3 0D5 Port 4 7 Symbol RnFFEp Description Same alarm as the corresponding address 045, 075, 0A5 and 0D5 bit, except that this alarm state is latched.
Unused(np) Unused: This bit reads out as 0. Latched Tx Same alarms as the corresponding address 045, 075, 0A5 and 0D5 bits, Alarms(p) except that these alarm states are latched. RnFFEp Receive Port n FIFO Error: A 1 indicates that the receive FIFO for port n has overflowed or underflowed. The FIFO is reset automatically. Other than an alarm indication, no action is taken.
6 5 4
Unused(np) Unused: This bit reads out as 0. ANAnOOLp PRBS Analyzer Out of Lock for Port n: A 1 indicates that the internal PRBS Analyzer is out of lock. TAnFEp Transmit A Add Bus Port n FIFO Error: A 1 indicates that the A Add bus transmit FIFO has overflowed or underflowed. The FIFO is recentered and is held reset for up to two multiframes automatically. The VT AIS payload will be transmitted via the add bus when the FIFO error occurs. Transmit B Add Bus Port n FIFO Error: A 1 indicates that the B Add bus transmit FIFO has overflowed or underflowed. The FIFO is recentered and is held reset for up to two multiframes automatically. The VT AIS payload will be transmitted via the add bus when the FIFO error occurs. Transmit Port n Loss Of Signal: An alarm occurs when there are no signal transitions detected on the positive rail or negative rail for a period of 256 consecutive pulse positions. Recovery occurs when there are at least 32 transitions counted for 256 consecutive pulse positions. For an NRZ signal, this alarm is active when a low occurs on the external transmit loss of signal indication lead TLOSpn, which is shared with the TNIpn lead. Transmit Port n Loss Of Clock: A 1 indicates that the transmit clock (TCIpn) for port n has stuck high or low for 6 or more clock cycles. Recovery occurs on the first clock transition.
3
TBnFEp
2
TnLOSp
1
TnLOCp
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 045 Port 1 075 Port 2 0A5 Port 3 0D5 Port 4 (cont.) 046 Port 1 076 Port 2 0A6 Port 3 0D6 Port 4 Bit 0 Symbol TnDAISp Description
E1Mx16 TXC-04216
Transmit Port n AIS Detected: A 1 indicates that line AIS (0 or 1 zeros in 256 bits) has been detected in the bit stream for port n. Recovery occurs when there are 3 or more zeros in 256 bits. Other than reporting the alarm, no action is taken. Transmit Port n Coding Violation Counter: Low order byte of a 16-bit saturating counter which counts the number of coding errors that have occurred in the HDB3 line code. During a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. This counter is cleared on a reset pulse, any RESETp, RnSETSp or RnSETCp control bit = 1, or when its low order byte is read. This low order byte must be read before the high order byte for the same port, which is located in the following address. Transmit Port n Coding Violation Counter: High order byte of an 16bit saturating counter which counts the number of coding errors that have occurred in the HDB3 line codes. During a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. This counter is cleared on a reset pulse, any RESETp, RnSETSp or RnSETCp control bit = 1, or when its low order byte is read. This high order byte must be read after the low order byte for the same port, which is located in the preceding address, but before the next read of the low order byte for any port. (Reading the low order byte for any port causes a simultaneous transfer of the contents of the high order byte for the same port into a high order byte memory location that is common to all four ports. When any high order byte is read, the data output from the high order byte address is the content of this common memory location, not the current content of the addressed high order byte.)
7-0
Coding Violation Counter Low Order Byte(np)
047 Port 1 077 Port 2 0A7 Port 3 0D7 Port 4
7-0
Coding Violation Counter High Order Byte(np)
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
PORT n - OPERATIONS (CONTROL) REGISTER DESCRIPTIONS (p=1-4) Address 048 Port 1 078 Port 2 0A8 Port 3 0D8 Port 4 Bit 7-5 4 Symbol Description
E1Mx16 TXC-04216
Unused(np) Unused: These bits must be written to 0. 1BnRDIp 1-Bit/3-Bit RDI Selection for Port n: When set to 0, the selected port will function as a 3-Bit enhanced RDI. When set to a 1, the selected port will function as 1-Bit RDI. J2 Transmit Message Enable for Port n: A 1 enables a microprocessor-written message to be transmitted. A 0 disables the transmission of the J2 message from RAM. Instead, the J2 byte is transmitted as 00H. J2 Message Size Segment for Port n: Works in conjunction with the J2nCOMp bit according to the following table: J2nSIZEp J2nCOMp 0 0 Action Transmit and receive J2 message segments are configured for a 16-byte message size. Microprocessor reads 16-byte segment. J2 comparison circuit and alarms are disabled. Transmit and receive J2 message segments are configured for a 16-byte message size. Trail Trace message comparison circuit enabled. Transmit and receive J2 message segments are configured for a 64-byte message size. Microprocessor reads 64-byte segment. J2 comparison circuit and alarms are disabled. The Tandem Connection feature must be disabled by setting TCnENp=0.
3
J2nTENp
2
J2nSIZEp
0
1
1
X
1 0
J2nCOMp J2nAISEp
J2 Message Comparison Enable Bit for Port n: Works in conjunction with the J2nSIZEp control bit according to the table given above. J2 AIS/RDI/TC Alarm Enable for Port n: A 1 enables Receive E1 AIS, a Remote Connectivity Defect Indication, and both of the TC alarms (TCnODIp, TCnRDIp) to be transmitted when either an AnJ2TIMp/ BnJ2TIMp or an AnJ2LOLp/BnJ2LOLp occurs. The AIS, RDI and TC alarm generated depend on the bus side selected.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 050 Port 1 080 Port 2 0B0 Port 3 0E0 Port 4 Bit 7 Symbol FnLBKp Description
E1Mx16 TXC-04216
Facility Loopback: A 1 enables an E1 facility (side) loopback for port n. The E1 transmit clock and data output signals are looped back internally as the E1 receive clock and data input signals. The external E1 receive input signals are disabled. The E1 transmit clock and data output signals are provided at the interface. Line Loopback: A 1 enables an E1 line (side) loopback for port n. The receive E1 clock and data output signals are looped back internally as the E1 transmit input signals. The external E1 transmit clock and data input signals are disabled. The E1 receive clock and data output signals are provided at the interface. Send Receive E1 Line AIS for Port n: A 1 enables an E1 AIS (unframed all ones signal) to be inserted into the receive data stream for port n independent of the status of the internal alarms. Transmit E1 Line AIS for Port n: A 1 enables an E1 AIS (unframed all ones signal) to be inserted into the transmit data stream for port n independent of the status of the internal alarms. Transmit VT AIS for the TU/VT Selected for Port n: A 1 enables a TU/ VT AIS to be transmitted for the TU/VT selected. A TU/VT AIS consists of all ones in the entire TU/VT, including bytes V1 through V4. Transmit Port n RFI (Remote Failure Indication): A 1 enables an RFI alarm to be transmitted (bit 4 in the V5 byte is set to 1). Transmit Port n RDIS (Remote Server Defect Indication): A 1 enables an RDIS to be transmitted (bit 8 in the V5 byte is set to 1, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 101). Transmit Port n RDIP (Remote Payload Defect Indication): A 1 enables an RDIP to be transmitted (bit 8 in the V5 byte is set to 0, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 010).
6
LnLBKp
5
RnAISp
4
TnAISp
3
TnVTAISp
2 1
TnRFIp TnRDISp
0
TnRDIPp
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 051 Port 1 081 Port 2 0B1 Port 3 0E1 Port 4 Bit 7 6 5 Symbol TCnRDIp TCnODIp TCnAISp Description
E1Mx16 TXC-04216
Tandem Connection RDI Generation for Port n: A 1 enables a TC RDI to be generated (bit 8 in frame 73 is a 1). Tandem Connection ODI Generation for Port n: A 1 enables a TC ODI to be generated (bit 7 in frame 74 is a 1). Tandem Connection AIS Indication Transmitted for Port n: A 1 enables a TC AIS indication to be generated (bit 4 in the N2 (Z6) byte is a 1). Tandem Connection Feature Enable for Port n: A 1 enables the TU Tandem Connection Feature (J2nSIZEp must be 0). A 0 disables the tandem connection feature. In the receive direction all TC alarms are disabled. In the transmit direction, bits 3 through 8 in the N2(Z6) byte are transmitted as 0 while bits 1 and 2 still contain the calculated BIP-2. Tandem Connection Remote Defect Indication Enable for Port n: As explained in Note 1, a 1 enables internal defined tandem connection alarms to send a TC RDI (bit 8 in frame 73). For example, a TC RDI for port 1 is generated: - When TC enable (TC1ENp) and TC RDI enable (TC1REp) are 1 and any of: - Loss Of Pointer Alarm (A1LOPp, B1LOPp) - TU AIS Alarm (A1AISp, B1AISp) - Drop Bus AIS Alarm (AsUAISIp, BsUAISIp) when HEAISEp is 1 - Drop Bus H4 Alarm (AsDH4Ep, BsDH4Ep) when DV1SELp is 1 - Unequipped signal label (A1UNEQp, B1UNEQp) when UQAEp is 1 - Mismatch signal label (A1SLERp, B1SLERp) - J2 Loss Of Lock Alarm (A1J2LOLp, B1J2LOLp) when J21AISEp is 1 - J2 Mismatch Alarm (A1J2TIMp, B1J2TIMp) when J21AISEp is 1 - TC Unequipped Alarm (A1TCUQp, B1TCUQp) - TC Loss Of Lock Alarm (A1TCLLp, B1TCLLp) - TC Mismatch Alarm (A1TCTMp, B1TCTMp) - TC Loss Of Multiframe Alarm (A1TCLMp, B1TCLMp) - A 1 written to TC1RDIp (where s is the STS-1 or AU-3 identifier, 1-3 or A-C) - When TC enable (TC1ENp) is a 1 and TC RDI enable (TC1REp) is 0 and: - A 1 written to TC1RDIp.
4
TCnENp
3
TCnREp
Note 1: In determining whether to send TC ODI or TC RDI, it is necessary to sample certain alarm conditions. Since TC ODI or TC RDI are sent only once for every 38 ms multiframe, it is conceivable that these alarms may toggle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 051 Port 1 081 Port 2 0B1 Port 3 0E1 Port 4 (cont.) Bit 2 Symbol TCnOEp Description
E1Mx16 TXC-04216
Tandem Connection Outgoing Defect Indication Enable for Port n: As explained in Note 1, a 1 enables internal defined tandem connection alarms to send a TC ODI (bit 7 in frame 74). For example, a TC ODI for port 1 is generated: - When TC enable (TC1ENp) and TC ODI enable (TC1OEp) are 1 and any of: - Loss Of Pointer Alarm (A1LOPp, B1LOPp) - TU AIS Alarm (A1AISp, B1AISp) - Drop Bus AIS Alarm (AsUAISIp, BsUAISIp) when HEAISEp is 1 - Drop Bus H4 Alarm (AsDH4Ep, BsDH4Ep) when DV1SELp is 1 - Unequipped signal label (A1UNEQp, B1UNEQp) when UQAEp is 1 - Mismatch signal label (A1SLERp, B1SLERp) - J2 Loss Of Lock Alarm (A1J2LOLp, B1J2LOLp) when J21AISEp is 1 - J2 Mismatch Alarm (A1J2TIMp, B1J2TIMp) when J21AISEp is 1 - TC Unequipped Alarm (A1TCUQp, B1TCUQp) - TC AIS alarm (A1TCAISp, B1TCAISp) - TC Loss Of Lock Alarm (A1TCLLp, B1TCLLp) - TC Mismatch Alarm (A1TCTMp, B1TCTMp) - TC Loss Of Multiframe Alarm (A1TCLMp, B1TCLMp) - A 1 written to TC1ODIp. (where s is the STS-1 or AU-3 identifier, 1-3 or A-C) - When TC enable (TC1ENp) is a 1 and TC ODI enable (TC1OEp) is 0 and: - A 1 written to TC1ODIp.
1 0
TCnAENp TnRDICp
Tandem Connection Line AIS Enable for Port n: A 1 enables internal receive TC alarms to generate receive E1 line AIS. Transmit Port n RDIC (Remote Connectivity Defect Indication): A 1 enables an RDIC to be transmitted (bit 8 in the V5 byte is set to 1, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 110). Reset Port n Selected Functions: A 1 will clear the alarms, reset the performance counters to 0, and re-initialize the FIFOs associated with port n. The control bits for port n are not reset. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. Reset Port n Performance Counters: A 1 resets the performance counters to 0 for port n. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. Transmit Port n BIP-2 Error Mask (Force BIP-2 Error): A 1 causes bits 1 and 2 (the BIP-2 value) in the V5 byte to be inverted from the calculated value and transmitted for one frame. This bit is self-clearing, and will reset to 0 after the single error is transmitted.
052 Port 1 082 Port 2 0B2 Port 3 0E2 Port 4
7
RnSETSp
6
RnSETCp
5-2 1
Unused(np) Unused: These bits must be written to 0. TnFB2p
Note 1: In determining whether to send TC ODI or TC RDI, it is necessary to sample certain alarm conditions. Since TC ODI or TC RDI are sent only once for every 38 ms multiframe, it is conceivable that these alarms may toggle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 052 Port 1 082 Port 2 0B2 Port 3 0E2 Port 4 (cont.) 053 Port 1 083 Port 2 0B3 Port 3 0E3 Port 4 Bit 0 Symbol TnFFBp Description
E1Mx16 TXC-04216
Transmit Port n FEBE Error Mask (Force FEBE Error): A 1 causes bit 3 (the FEBE value) of the V5 byte to be transmitted as a 1. This control bit is self-clearing, and will reset to 0 after the V5 byte has been transmitted. Please note that if a FEBE is being sent as a result of a receive BIP-2 error, the FEBE error set by this bit is transmitted afterwards. A Drop Bus Port n Microprocessor-Written Mismatch Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/VT selected. Bit 2 in this register corresponds to bit 7 in the V5 byte. The bits written into this register are compared against the received signal for a mismatch signal label alarm. B Drop Bus Port n Microprocessor-Written Mismatch Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/VT selected. Bit 2 in this register corresponds to bit 7 in the V5 byte. The bits written into this register are compared against the received signal for a mismatch signal label alarm. Transmit Port n Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/ VT selected for transmission. Bit 2 in this register corresponds to bit 7 in the V5 byte.
7-3 2-0
Unused(np) Unused: These bits must be written to 0. AnUPSLp
054 Port 1 084 Port 2 0B4 Port 3 0E4 Port 4
7-3 2-0
Unused(np) Unused: These bits must be written to 0. BnUPSLp
055 Port 1 085 Port 2 0B5 Port 3 0E5 Port 4 058 Port 1 088 Port 2 0B8 Port 3 0E8 Port 4
7-3 2-0
Unused(np) Unused: These bits must be written to 0. Tn TX Label(p)
7-4
Transmit K4 (Z7) Value Port n: The value written into bits 7, 6, 5, 4 and Transmit K4 (Z7) Byte 0 in this register is transmitted when control bit TOBWZp is 0. Bits 3, 2, Value(np) and 1 are assigned for the RDI indicators and cannot be written to in this register. Bit 7 corresponds to bit 1 in the K4 (Z7) byte. Unused(np) Unused: These bits must be written to 0. Transmit K4 (Z7) Value Port n: The value written into bits 7, 6, 5, 4 and Transmit K4 (Z7) Byte 0 in this register is transmitted when control bit TOBWZp is 0. Bits 3, 2, Value(np) and 1 are assigned for the RDI indicators and cannot be written to in this register. Bit 0 corresponds to bit 8 in the K4 (Z7) byte. Transmit O-bits(np) Transmit O Bits Port n: The value written into this register is transmitted when control bit TOBWZp is 0. Bits 7 through 4 correspond to bits 3 through 6 in the second justification control byte. Bits 3 through 0 correspond to bits 3 through 6 in the first justification control byte. Transmit V4 Byte Port n: The value written into this register will be transmitted as the V4 byte. Bits 7-0 of the register correspond to bits 1-8 of the V4 byte.
3-1 0
059 Port 1 089 Port 2 0B9 Port 3 0E9 Port 4 511 Port 1 591 Port 2 611 Port 3 691 Port 4
7-0
7-0
Transmit V4 Byte(np)
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
PORT n - A AND B DROP J2 AND N2 (Z6) MESSAGE SEGMENTS (p=1-4) Address 140 Port 1 240 Port 2 340 Port 3 440 Port 4 to 17F Port 1 27F Port 2 37F Port 3 47F Port 4 Bit 7-0 Symbol A Side Receive J2 and N2 (Z6) Message Segments(np) Description
E1Mx16 TXC-04216
A Side Drop J2 and N2 (Z6) Message Segments: The following locations store the received 64-byte J2 message when control bit J2nSIZEp is a 1, and the received 16-byte J2 message and microprocessor-written 16-byte J2 message when J2nSIZEp is a 0, and the received 16-byte N2 (Z6) trail trace message and microprocessor-written 16-byte N2 (Z6) message used for message mismatch comparison. Location X40-X7F Message Segment J2 Message size configured for 64 bytes. The 64-byte message is written into memory with no specific starting address location. The N2 (Z6) tandem connection feature is disabled. Received 16-byte J2 message segment. Microprocessor-written 16-byte J2 message segment. The starting address of the message must be written to location X50 (multiframe value of 1). Received 16-byte N2 (Z6) message segment. Microprocessor-written 16-byte N2 (Z6) message segment. The starting address of the message must be written to location X70 (multiframe value of 1).
X40-X4F X50-X5F
X60-X6F X70-X7F
1C0 Port 1 2C0 Port 2 3C0 Port 3 4C0 Port 4 to 1FF Port 1 2FF Port 2 3FF Port 3 4FF port 4
7-0
B Side Receive J2 and N2 (Z6) Message Segments(np)
B Side Drop J2 and N2 (Z6) Message Segments: The following locations store the received 64-byte J2 message when control bit J2nSIZEp is a 1, and the received 16-byte J2 message and microprocessor-written 16-byte J2 message when J2nSIZEp is a 0, and the received 16-byte N2 (Z6) trail trace message and microprocessor-written 16-byte N2 (Z6) message used for message mismatch comparison. Location XC0-XFF Message Segment J2 Message size configured for 64 bytes. The 64-byte message is written into memory with no specific starting address location. The N2 (Z6) tandem connection feature is disabled. Received 16-byte J2 message segment. Microprocessor-written 16-byte J2 message segment. The starting address of the message must be written to location XD0 (multiframe value of 1). Received 16-byte N2 (Z6) message segment. Microprocessor-written 16-byte N2 (Z6) message segment. The starting address of the message must be written to location XF0 (multiframe value of 1).
XC0-XCF XD0-XDF
XE0-XEF XF0-XFF
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
Address 540 Port 1 5C0 Port 2 640 Port 3 6C0 Port 4 to 57F Port 1 5FF Port 2 67F Port 3 6FF Port 4 Bit 7-0 Symbol Transmit J2 and N2 (Z6) Message Segments(np) Description
E1Mx16 TXC-04216
Transmit J2 and N2 (Z6) Message Segments: The following locations store the transmitted 64-byte J2 message when control bit J2nSIZEp is a 1, and the transmitted 16-byte J2 and N2 (Z6) messages when J2nSIZEp is a 0. Location 540-57F (Port 1) 5C0-5FF (Port 2) 640-67F (Port 3) 6C0-6FF (Port 4) 540-54F (Port 1) 5C0-5CF (Port 2) 640-64F (Port 3) 6C0-6CF (Port 4) 560-56F (Port 1) 5E0-5EF (Port 2) 660-66F (Port 3) 6E0-6EF (Port 4) Message Segment J2 Message size configured for 64 bytes. The 64-byte message is transmitted from no specific starting address. The tandem connection feature is disabled. J2 Message size configured for 16 bytes. The 16-byte message is transmitted with no specific starting address.
N2 (Z6) Message size configured for 16 bytes. The 16-byte message is transmitted with no specific starting address.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET APPLICATION EXAMPLES
E1Mx16 TXC-04216
The E1Mx16 can be used in a wide range of telecommunication and data communication applications: * Terminal Multiplexers, with bus redundancy * Add/Drop Multiplexers for TU/VT tributaries * Add/Drop Multiplexers for protection rings
The following diagram illustrates a typical application using the E1Mx16. WEST TERMINAL STM-1/STS-3 PHAST-3N (TXC-06103) and Bus Drivers/Receivers
B DROP B ADD A DROP A ADD MICROPROCESSOR BUS
EAST TERMINAL PHAST-3N (TXC-06103) and Bus Drivers/Receivers
STM-1/STS-3
E1Mx16 TXC-04216
E1Mx16 TXC-04216
Up to 63 E1 channels per STS-3 Figure 25. Typical Application using the E1Mx16 The application diagram in Figure 25 shows a fully configured bidirectional add/drop fiber multiplexer. Using the full four-bus capability of the E1Mx16, channels may be dropped from either direction with full time slot reuse in both directions. Using only the B Drop and the A Add buses provides add/drop service back to the network source only, and eliminates the block marked "East Terminal" for a terminal configuration.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET PACKAGE INFORMATION
E1Mx16 TXC-04216
The E1Mx16 device is packaged in a 388-lead plastic ball grid array package suitable for surface mounting, as illustrated in Figure 26.
E E2 Bottom View
-E1-
b
51 51 51 58 58 58 5 51 51 51 51 58 58 5 5 51 51 51 51 58 58 5 5 51 51 51 51 58 58 5 5 5 5 5 5 5 5 5 5 5 5 5 5 51 51 51 51 51 51 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 AC AD AB 51 51 51 51 5 5 5 5 51 51 51 51 5 5 5 5 51 51 51 51 5 5 5 5 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TRANSWITCH
TXC-04216AIBG
D D2 Note 2 E1/4
-D1-
51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 AE AF
e
D1/4
AA Y W V U
TRPNML
KJH GFE D CBA
A3
A2
A A1
51 5 51 5 51 5 51 5
Dimension (Note 1) A (Nom) Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. Package corner may not be a 90 angle. A1 A2 (Nom) A3 (Nom) b (Ref.) D D1 (Nom) D2 E E1 (Nom) E2 e (Ref.)
Min 2.53 0.50 1.17 0.72 0.76 34.90 31.75 32.40 34.90 31.75 32.40 1.27
Max
0.70
35.10 32.60 35.10 32.60
Figure 26. E1Mx16 TXC-04216 388-Lead Plastic Ball Grid Array Package - 135 PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET ORDERING INFORMATION
E1Mx16 DEVICE Part Number: TXC-04216AIBG 388-Lead Plastic Ball Grid Array Package
E1Mx16 TXC-04216
E1Mx16 MICROCODE (uses QE1M microcode) Part Number: TXC-04252-SCAA-FDPE
RELATED PRODUCTS
TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). This device is similar to the SYN155. It has both clock and data outputs on the line side. TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). This is a dual-mode device, which can be configured either to emulate the TXC-03001 device or to provide additional capabilities. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line and path overhead processing for STM-1/STS-3/ STS-3c signals. Compliant with ANSI and ITU-T standards. TXC-03011, SOT-1E VLSI Device (SONET STS-1 Overhead Terminator). This device provides extended features relative to the 84-lead TXC-03001 and TXC-03001B SOT-1 devices, and it has a 144-lead package. TXC-04252, QE1M VLSI Device (Quad E1 to AU-4/VT2 or TU-12 Async MapperDesync). Interconnects four E1 signals with any four asynchronous mode VT2 or TU-12 tributaries carried in SDH AU-4/AU-3 rate payload interface. TXC-06103, PHAST-3N VLSI Device (SONET STM-1, STS-3 or STS-3c Overhead Terminator). The PHAST-3N VLSI device provides a Telecom Bus interface for downstream devices and operates from a power supply of 3.3 volts. It combines the functions of the SOT-3 and SYN155C devices.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET STANDARDS DOCUMENTATION SOURCES
E1Mx16 TXC-04216
Telecommunication technical standards and reference documentation may be obtained from the following organizations:
ANSI (U.S.A.): American National Standards Institute 11 West 42nd Street New York, New York 10036 The ATM Forum (U.S.A., Europe, Asia): 2570 West El Camino Real Suite 304 Mountain View, CA 94040 ATM Forum Europe Office Av. De Tervueren 402 1150 Brussels Belgium ATM Forum Asia-Pacific Office Hamamatsu-cho Suzuki Building 3F 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan Bellcore (See Telcordia) CCITT (See ITU-T) EIA (U.S.A.): Electronic Industries Association Global Engineering Documents 7730 Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France Tel: 4 92 94 42 22 Fax: 4 92 94 43 33 Web: www.etsi.org Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: (650) 949-6700 Fax: (650) 949-6705 Web: www.atmforum.com Tel: (212) 642-4900 Fax: (212) 302-1286 Web: www.ansi.org
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
GO-MVIP (U.S.A.): The Global Organization for Multi-Vendor Integration Protocol (GO-MVIP) 3220 N Street NW, Suite 360 Washington, DC 20007 ITU-T (International): Publication Services of International Telecommunication Tel: 22 730 5111 Union Telecommunication Standardization Sector Fax: 22 733 7256 Place des Nations, CH 1211 Web: www.itu.int Geneve 20, Switzerland MIL-STD (U.S.A.): DODSSP Standardization Documents Ordering Desk Building 4 / Section D 700 Robbins Avenue Philadelphia, PA 19111-5094 PCI SIG (U.S.A.): PCI Special Interest Group 2575 NE Kathryn Street #17 Hillsboro, OR 97124 Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (215) 697-2179 Fax: (215) 697-1462 Web: www.dodssp.daps.mil Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) Fax: (508) 650-1375 Web: www.mvip.org
Telcordia (U.S.A.): Telcordia Technologies, Inc. Attention - Customer Service 8 Corporate Place Piscataway, NJ 08854 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsu-cho Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET LIST OF DATA SHEET CHANGES
E1Mx16 TXC-04216
This change list identifies those areas within this updated E1Mx16 Data Sheet that have significant differences relative to the previous and now superseded E1Mx16 Data Sheet: Updated E1Mx16 Data Sheet: Previous E1Mx16 Data Sheet:
PRELIMINARY Ed. 2, October 2000 PRODUCT PREVIEW Ed. 1, December 1999
The page numbers indicated below of this updated Data Sheet include changes relative to the previous Data Sheet.
Page Number of Updated Data Sheet All All 2-3 25
Summary of the Change Changed edition number and date. Changed Data Sheet status markings and explanatory text on pages 1 and 141 from PRODUCT PREVIEW to PRELIMINARY. Changed Table of Contents and List of Figures. Added Latch Up specification to the Absolute Maximum Ratings and Environmental Limitations Table. Changed the value in the column labeled "Max" in the Thermal Characteristics Table. Changed Min value for Symbol tH in table of Figure 4. Changed names of the second and sixth signals from top in Figure 6. In the table, added "/DPAR" and /parity to "Parameter" text on third, fourth, tenth, eleventh and fourteenth rows, changed value of capacitance in the "Load" column in four places. Changed names of the second and sixth signals from the top in Figure 7. In the table added /DPAR and /parity to the parameter text on the third, fourth tenth, eleventh and fourteenth rows, changed value of capacitance in the "Load" column in four places. Changed name of fourth signal from the top in Figure 8. In the table, added "/APAR" and /parity to "Parameter" text on the seventh, eighth and eleventh rows, changed value of capacitance in the "Load" column in three places. Changed name of fourth signal from the top in Figure 9. In the table, added "/APAR" and /parity to "Parameter" text on the seventh, eighth and eleventh rows, changed value of capacitance in the "Load" column in three places. Added TRS (INPUT) signal diagram to bottom of Figure 14. Added "TRS Pulse Width" row to bottom of table. In the "Add and Drop Bus V1 Reference Selection for Group P" table, Changed the entry in the DV1REFp column to 0 in the first two rows labeled "Drop bus timing selected ". Switched position of the words "Connectivity" and "Payload" in the third line of the paragraph "V5 and K4 (Z7) Byte Coding (for 3-Bit RDI)" Changed the last line of the note on the bottom of the page.
29 31
32
33
34
43 51
62 63
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
Page Number of Updated Data Sheet 77-81 86 88 99 102 105 137 - 138 139-140
Summary of the Change Added Jitter Measurements section. Deleted note below the Boundary Scan Operation section. Deleted 24 page Boundary Scan Chain table. Changed Boundary Scan Chain description paragraph and added footnotes. Shaded the first entry in the column "Bit 4", symbol "1BnRDIp" of the operations and control register table. Changed text for the description of the "Add Bus Delay" for Address 11, Bit 7, Symbol "ABDp". Changed text for description of address 013, Bit 5, Symbol DV1REFp in the common registers table. Changed Standards Documentation Sources section. Added List of Data Sheet Changes section.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
DATA SHEET
E1Mx16 TXC-04216
- NOTES -
TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
PRELIMINARY information documents contain information on products in the sampling, preproduction or early production phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product.
- 141 -
PRELIMINARY TXC-04216-MB Ed. 2, October 2000
Engines for Global Connectivity
TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com
- 142 -
DATA SHEET DOCUMENTATION UPDATE REGISTRATION FORM
E1Mx16 TXC-04216
If you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the Marketing Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453), or by e-mail (info@txc.com), or by telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www.transwitch.com). Name: ________________________________________________________________________________ Company: ___________________________________________ Title: ______________________________ Dept./Mailstop: __________________________________________________________________________ Street: ________________________________________________________________________________ City/State/Zip: __________________________________________________________________________ If located outside U.S.A., please add - Country: ________________ Postal Code: ___________________ Telephone: ________________________ Ext.: _____________ Fax: __________________________
E-mail: ________________________________________________ Please provide the following details for the managers in charge of the following departments at your company location. Department Company/Division Engineering Marketing Title __________________ __________________ __________________ Name __________________ __________________ __________________
Please describe briefly your intended application(s) and indicate whether you would like to have a TranSwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________
Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453.
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PRELIMINARY TXC-04216-MB Ed. 2, October 2000
Engines for Global Connectivity
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3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
First Class Postage Required
TranSwitch Corporation
Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
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Please complete the registration form on this back cover sheet, and mail or fax it, if you wish to receive updated documentation on selected TranSwitch products as it becomes available.
TranSwitch Corporation
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3 Enterprise Drive
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Shelton, CT 06484 USA
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Tel: 203-929-8810
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Fax: 203-926-9453
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www.transwitch.com

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